DMOS power transistors with reduced number of contacts using integrated body-source connections

• US 5,410,170 A
• Filed: 04/14/1993
• Issued: 04/25/1995
• Est. Priority Date: 04/14/1993
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Bulucea, Constantin, Rossen, Rebecca
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/047,723
• Time in Patent Office: 741 Days
• Field of Search: 257/327, 257/329, 257/330, 257/331, 257/332, 257/334, 257/344, 257/401
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Claims

1. A closed DMOS field effect transistor cell formed in a semiconductor substrate, having a gate region, a source region, a drain region, and a body region, said DMOS field effect transistor cell having a portion exposed at a surface of said semiconductor substrate, wherein said exposed portion has the topology of an elongated hexagon.

2. The closed transistor cell of claim 1 wherein the body region and the source region each having a portion exposed to a surface of said semiconductor substrate and wherein said source region and said body region are connected electrically.

3. A high power transistor structure comprising a plurality of DMOS field effect transistor cells connected in parallel, each of said DMOS field effect transistor cells being the closed DMOS field effect transistor cell of claim 1.

4. A closed DMOS field effect transistor cell as in claim 1, wherein said source region and said body region are formed in an epitaxial layer in said semiconductor substrate.

5. A closed DMOS field effect transistor cell as in claim 1, wherein said gate region comprises a trench structure forming the perimeter of said elongated hexagon.

6. A closed DMOS field effect transistor cell as in claim 5, wherein said body region and said trench structure extend respectively to first and second depths in said semiconductor substrate, wherein said first depth is greater than said second depth.

7. A closed DMOS field effect transistor cell as in claim 1, wherein said gate region comprises a polysilicon filled trench.

8. A closed DMOS field effect transistor cell as in claim 1, wherein said drain region comprises a lightly-doped drift region and a heavily-doped region.

9. A closed DMOS field effect transistor cell as in claim 1, said closed DMOS field effect transistor having an on-resistance in which the resistance of said body region is less than the resistance in said drain region.