Ripple-free phase detector using two sample-and-hold circuits

• US 5,410,195 A
• Filed: 10/29/1992
• Issued: 04/25/1995
• Est. Priority Date: 10/31/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ichihara, Masaki
• Primary Examiner(s): WOLFE JR, WILLIS RAY
• Application Number:
  US07/968,575
• Time in Patent Office: 908 Days
• Field of Search: 307/514, 307/516, 307/519, 307/526, 307/353, 328/133, 328/134, 328/155
• US Class Current: 327/10
• CPC Class Codes: H03D 13/006 and by sampling this signal by narrow pulses obtained from the second oscillation

Abstract

A phase detector comprises a ramp voltage generator for receiving a reference pulse of a constant frequency and an input pulse and producing a ramp voltage proportional to the phase difference between these pulses. A first sample-and-hold circuit samples the ramp voltage in response to a sampling pulse and holds the sampled voltage. To eliminate ripple component, a second sample-and-hold circuit is provided, which is also responsive to the sampling pulse for sampling a voltage from a constant voltage source and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor where the voltage difference between the two input voltages is detected. Ripple components generated by the two sample-and-hold circuits are cancelled out by the subtractor.

Claims

1. A phase detector comprising:

ramp voltage generating means for receiving a reference pulse of a predetermined constant frequency and an input pulse and developing a ramp voltage proportional to a phase difference between the reference pulse and said input pulse;

means for generating a sampling pulse subsequent to the reference pulse;

first sample-and-hold means for sampling said ramp voltage in response to the sampling pulse;

second sample-and-hold means for sampling a constant voltage in response to said sampling pulse; and

means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold means.

2. A phase detector as claimed in claim 1, further comprising:

delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse; and

second ramp voltage generating means for receiving said first and second reference pulses and developing said constant voltage proportional to said prescribed interval.

3. A phase detector comprising:

a first integrated-circuit capacitor;

charging means for receiving a reference pulse of a predetermined constant frequency and an input pulse, and drawing a current at a constant rate into the first integrated-circuit capacitor during an interval corresponding to a phase difference between the reference pulse and said input pulse to develop a ramp voltage in said first integrated-circuit capacitor;

a first integrated-circuit sample-and-hold circuit connected to said first integrated-circuit capacitor;

second integrated-circuit sample-and-hold circuit connected to a source of constant voltage;

sampling means for causing said first and second integrated-circuit sample-and-hold circuits to sample said ramp voltage and said constant voltage, respectively, during an interval subsequent to said reference pulse; and

means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.

4. A phase detector as claimed in claim 3, wherein said source of constant voltage comprises:

delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse;

a second integrated-circuit capacitor; and

second charging means for receiving said first and second reference pulses and drawing a current at said constant rate into said second integrated-circuit capacitor during an interval corresponding to said prescribed interval.

5. A phase detector comprising:

a switching pulse source for receiving a first reference pulse of a predetermined constant frequency and an input pulse and producing said first charge timing pulse of duration corresponding to a phase difference between said first reference pulse and said input pulse, for receiving a second reference pulse of said predetermined constant frequency and producing a second charge timing pulse of constant duration corresponding to a phase difference between said first and second reference pulses, and for successively producing a sampling pulse and a discharge timing pulse during an interval following a trailing edge of said first reference pulse;

first and second identical constant current sources;

a first capacitor;

first switch means for drawing a current from the constant current source into the first capacitor in response to said first charge timing pulse and drawing a current from the first capacitor in response to said discharge timing pulse;

a first sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the first capacitor and holding the sampled voltage;

a second capacitor;

second switch means for drawing a current from the constant current source into the second capacitor in response to said second charge timing pulse and drawing a current from the second capacitor (8) in response to said discharge timing pulse;

a second sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the second capacitor and holding the sampled voltage; and

means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.