Differential amplifier circuit having offset cancellation and method therefor
First Claim
Patent Images
1. A single-ended to differential amplifier circuit, comprising:
- input sampling means for receiving an input signal, the input sampling means sampling the input signal and storing a first charge value corresponding to the input signal;
transfer means coupled to the input sampling means for transferring the first charge value;
an operational amplifier coupled to the transfer means for receiving the first charge value, the operational amplifier having an offset value and an error value;
an integration means coupled to the operational amplifier for integrating the first charge value, the integration means combining the first charge value, the offset value and the error value to generate an output value; and
a cancellation means coupled to the integration means and the operational amplifier, the cancellation means subtracting the offset value and the error value from the output value to produce a corrected output value, the cancellation means comprising;
a first switch for transferring a first portion of the offset voltage and the error value from the integration means to a first output of the operational amplifier, the first switch having a first terminal coupled to the second terminal of the first feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the second output of the operational amplifier; and
a second switch for transferring a second portion of the offset voltage and the error value from the integration means to a second output of the operational amplifier, the second switch having a first terminal coupled to the second terminal of the second feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the first output of the operational amplifier;
the first portion of the offset voltage and the error value and the second portion of the offset voltage and the error value being used to generate the corrected output value.
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Abstract
The present invention provides a circuit (10) and method for sampling a single-ended signal and then converting the single-ended signal to a differential signal. After the single-ended signal is converted to a differential signal, then the offset voltage and low frequency noise of an operational amplifier (38) are subtracted from the differential signal using analog techniques. The subtraction operation effectively removes an operational amplifier'"'"'s offset voltage and a low frequency noise from being a source of error in the differential output signal of the circuit.
211 Citations
19 Claims
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1. A single-ended to differential amplifier circuit, comprising:
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input sampling means for receiving an input signal, the input sampling means sampling the input signal and storing a first charge value corresponding to the input signal; transfer means coupled to the input sampling means for transferring the first charge value; an operational amplifier coupled to the transfer means for receiving the first charge value, the operational amplifier having an offset value and an error value; an integration means coupled to the operational amplifier for integrating the first charge value, the integration means combining the first charge value, the offset value and the error value to generate an output value; and a cancellation means coupled to the integration means and the operational amplifier, the cancellation means subtracting the offset value and the error value from the output value to produce a corrected output value, the cancellation means comprising; a first switch for transferring a first portion of the offset voltage and the error value from the integration means to a first output of the operational amplifier, the first switch having a first terminal coupled to the second terminal of the first feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the second output of the operational amplifier; and a second switch for transferring a second portion of the offset voltage and the error value from the integration means to a second output of the operational amplifier, the second switch having a first terminal coupled to the second terminal of the second feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the first output of the operational amplifier; the first portion of the offset voltage and the error value and the second portion of the offset voltage and the error value being used to generate the corrected output value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for operating an amplifier circuit comprising the steps of:
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receiving an input signal; sampling the input signal and storing a first charge value corresponding to the input signal; transferring the first charge value to an operational amplifier, the operational amplifier having an offset value and an error value; integrating the first charge value using an integration circuit, the offset value and an error value to generate an output value; transferring a first portion of the offset voltage and the error value from the integration circuit to a first output of the operational amplifier using a first switch; and transferring a second portion of the offset voltage and the error value from the integration circuit to a second output of the operational amplifier using a second switch; the first portion of the offset voltage and the error value and the second portion of the offset voltage and the error value being subtracted from the output value to generate a corrected output value. - View Dependent Claims (9, 10, 11)
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12. A single-ended to differential amplifier circuit, comprising:
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a first switch having a first terminal for receiving an input signal, a second terminal for receiving a delayed first clock signal, and a third terminal; a first input capacitor having a first electrode coupled to the third terminal of the first switch and a second electrode; a second switch having a first terminal coupled to the second electrode of the first input capacitor, a second terminal for receiving a first clock signal, and a third terminal; a second input capacitor having a first electrode coupled to the third terminal of the second switch and a second electrode; a third switch having a first terminal for receiving an analog ground voltage, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the second electrode of the second input capacitor; a fourth switch having a first terminal coupled to the third terminal of the first switch, a second terminal coupled to a second clock signal, and a third terminal coupled to a reference ground voltage; a fifth switch having a first terminal coupled to the second electrode of the first input capacitor, a second terminal for receiving the second clock signal, and a third terminal coupled to a first input of an operational amplifier; a sixth switch having a first terminal coupled to the third terminal of the second switch, a second terminal for receiving the second clock signal, and a third terminal coupled to a second input of the operational amplifier; a seventh switch having a first terminal coupled to the third terminal of the third switch, a second terminal for receiving the second clock signal, and a third terminal for receiving the reference ground voltage; an eighth switch having a first terminal coupled to the first input of the operational amplifier, a second terminal for receiving the first clock signal, and a third terminal coupled to a first output of the operational amplifier; a first feedback capacitor having a first terminal coupled to the first input of the operational amplifier and a second terminal; a ninth switch having a first terminal coupled to the first output of the operational amplifier, a second terminal for receiving the second clock signal, and a third terminal coupled to the second terminal of the first feedback capacitor; a tenth switch having a first input coupled to the second input of the operational amplifier, a second terminal for receiving the first clock signal, and a third terminal coupled to a second output of the operational amplifier; a second feedback capacitor having a first terminal coupled to the second input of the operational amplifier and a second terminal; an eleventh switch having a first terminal coupled to the second output of the operational amplifier, a second terminal for receiving the second clock signal, and a third terminal coupled to the second terminal of the second feedback capacitor; a twelfth switch having a first terminal coupled to the second terminal of the first feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the second output of the operational amplifier; and a thirteenth switch having a first terminal coupled to the second terminal of the second feedback capacitor, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the first output of the operational amplifier. - View Dependent Claims (13, 14)
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15. A single-ended to differential amplifier circuit, comprising:
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input sampling means for receiving an input signal, the input sampling means sampling the input signal and storing a first charge value corresponding to the input signal, wherein the input sampling means comprises; a first switch having a first terminal for receiving the input signal, a second terminal for receiving a delayed first clock signal, and a third terminal for transferring the input signal in response to the delayed first clock signal; a first input capacitor having a first electrode coupled to the third terminal of the first switch and a second electrode, the first input capacitor storing the first charge value corresponding to a first portion of the input signal; a second switch having a first terminal coupled to the second electrode of the first input capacitor, a second terminal for receiving a first clock signal, and a third terminal; a second input capacitor having a first electrode coupled to the third terminal of the second switch and a second electrode, the second input capacitor storing a second charge value corresponding to a second proportion of the input signal; and a third switch having a first terminal for receiving an analog reference ground voltage, a second terminal for receiving the delayed first clock signal, and a third terminal coupled to the second electrode of the second input capacitor for transferring an analog ground voltage; transfer means coupled to the input sampling means for transferring the first charge value; an operational amplifier coupled to the transfer means for receiving the first charge value, the operational amplifier having an offset value and an error value; an integration means coupled to the operational amplifier for integrating the first charge value, the integration means combining the first charge value, the offset value and the error value to generate an output value; and a cancellation means coupled to the integration means and the operational amplifier, the cancellation means subtracting the offset value and the error value from the output value to produce a corrected output value. - View Dependent Claims (16, 17, 18, 19)
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Specification