Methods of controlling the erasing and writing of information in flash memory

• US 5,410,511 A
• Filed: 02/23/1994
• Issued: 04/25/1995
• Est. Priority Date: 02/24/1993
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Michiyama, Junji
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/200,497
• Time in Patent Office: 426 Days
• Field of Search: 365/218, 365/185, 365/900, 365/189.01
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

Abstract

In a flash memory, the value of an erasing voltage pulse is temporarily set so that information stored in all the memory cells is erased by means of the erasing voltage pulse. The value of the erasing voltage pulse is reset so that the highest threshold voltage of all the reduced voltages of the memory cells after erasing reaches a specified value or under and that the leakage current generated in memory cells on the same bit line reaches a specified limit value or under. With the application of the reset erasing voltage pulse to all the memory cells, the content of the flash memory is erased, thereby preventing the misreading of the information stored in the memory due to the leakage current generated in the memory cells.

Claims

1. A method of controlling the erasing of information in a flash memory, comprising the steps of:

setting the value of a control voltage pulse for reducing the threshold voltages of memory cells constituting the flash memory;

reducing the threshold voltages of all the memory cells with the application of said control voltage pulse;

checking an upper limit of all the reduced threshold voltages of said memory cells;

checking a leakage current generated in said memory cells on a same bit line; and

resetting the value of said control voltage pulse so that the highest threshold voltage of all the reduced threshold voltages of said memory cells is sufficiently lowered and that said leakage current generated in the memory cells on the same bit line reaches a specified limit value or under,

wherein the erasing of information in said flash memory is accomplished by applying said reset control voltage pulse to all said memory cells.

2. A method of controlling the erasing of information in a flash memory according to claim 1, wherein the leakage current is detected by means of a single ended sense amplifier of current detector type which is used for reading the information stored in the flash memory.

3. A method of controlling the writing of information in a flash memory, comprising the steps of:

setting the value of a control voltage pulse for reducing the threshold voltages of memory cells constituting the flash memory;

reducing the threshold voltage of a specific memory cell with the application of said control voltage pulse;

checking a magnitude of the reduced threshold voltage of said specific memory cell;

checking a leakage current generated in said specific memory cell; and

resetting the value of said control voltage pulse so that the reduced threshold voltage of said specific memory cell is sufficiently lowered and that said leakage current generated in said specific memory cell reaches a specified limit value or lower,

wherein the writing of information in said flash memory is accomplished by applying said reset control voltage pulse to said specific memory cell.

4. A method of controlling the writing of information in a flash memory according to claim 3, wherein the leakage current is detected by means of a single ended sense amplifier of current detector type which is used for reading the information stored in the flash memory.