Apparatus and method for determining a time that a system's main power was inactive

• US 5,410,581 A
• Filed: 05/02/1994
• Issued: 04/25/1995
• Est. Priority Date: 05/02/1994
• Status: Expired due to Term

• Current Assignee: Temic Automotive of North America, Incorporated (Continental AG)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hollenbeck, Neal W., Kang, David D.
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US08/236,850
• Time in Patent Office: 358 Days
• Field of Search: 377/28, 377/16, 328/129.1
• US Class Current: 377/28
• CPC Class Codes: G01R 31/007 using microprocessors or computers
• CPC Class Codes: G07C 3/04 using counting means or digital clocks
• CPC Class Codes: G07C 5/04 using counting means or digital clocks

Abstract

An apparatus and method for determining a time that a system'"'"'s main power was inactive includes a counter circuit (171) for accumulating transitions of a clock signal (149) while the system'"'"'s main power (117) is inactive. Preferably, another circuit (159, 125) determines a periodicity of the clock signal (149) after the system'"'"'s main power (117) transitions active. Then a computational circuit, preferably a microcontroller (129), determines the time (183) that the system'"'"'s main power (117) was inactive dependent on a number of transitions of the clock signal (149) accumulated by the counter circuit (171) when the system'"'"'s main power (119) was inactive and the determined periodicity of the clock signal (149) after the system'"'"'s main power (117) transitions active. Preferably, this apparatus and method are used in a vehicle to determine how long a time that an engine is turned off and to modify an engine control strategy dependent on that determined time.

Claims

1. An apparatus for determining a time that a system'"'"'s main power was inactive comprising:

clock means for providing a clock signal while the system'"'"'s main power is inactive, wherein the clock signal has transitions;

means for accumulating the transitions of the clock signal while the system'"'"'s main power is inactive;

means for determining a periodicity of the clock signal after the system'"'"'s main power transitions active; and

means for determining the time the system'"'"'s main power was inactive dependent on a number of accumulated transitions of the clock signal when the system'"'"'s main power was inactive and the determined periodicity of the clock signal after the system'"'"'s main power transitions active.

2. An apparatus in accordance with claim 1 wherein the means for determining comprises means for determining the time the system'"'"'s main power was inactive by multiplying the number of accumulated transitions of the clock signal when the system'"'"'s main power was inactive by the determined periodicity of the clock signal after the system'"'"'s main power transitions active.

3. An apparatus in accordance with claim 1 wherein the means for determining comprises means for determining the periodicity of the clock signal by determining an average periodicity dependent on more than one period of the clock signal.

4. An apparatus in accordance with claim 1 wherein the means for determining comprises means for determining a periodicity of the clock signal using a high-frequency system clock signal available after the system'"'"'s main power transitions active.

5. An apparatus for determining a time that a system'"'"'s main power was inactive comprising:

system clock means for providing a high-frequency clock signal when the system'"'"'s main power is active;

low-frequency clock means for providing a low-frequency clock signal independent of the activity of the system'"'"'s main power;

first counter means for accumulating transitions of the low-frequency clock signal while the system'"'"'s main power is inactive;

second counter means for accumulating transitions of the high-frequency clock signal dependent on a periodicity of the low-frequency clock signal when the system'"'"'s main power is active; and

computational means for determining the time the system'"'"'s main power was inactive dependent on a number of low-frequency clock signal transitions accumulated by the first counter means when the system'"'"'s main power was inactive and a number of accumulated transitions of the high-frequency clock signal when the system'"'"'s main power is active.

6. An apparatus in accordance with claim 5 wherein the computational means comprises means for determining the time the system'"'"'s main power was inactive by multiplying the number of low-frequency clock signal transitions accumulated by the first counter means when the system'"'"'s main power was inactive by the number of accumulated transitions of the high-frequency clock signal when the system'"'"'s main power is active.

7. An apparatus in accordance with claim 5 wherein the second counter means further comprises means for accumulating transitions of the high-frequency clock signal dependent on an integer multiple number of periods of the low-frequency clock signal when the system'"'"'s main power is active.

8. An apparatus in accordance with claim 5 further comprising means for resetting the first counter means when the system'"'"'s main power transitions from active to inactive.

9. An apparatus in accordance with claim 5 wherein the first counter means further comprises means for preventing the accumulation of transitions of the low-frequency clock signal when the first counter means has overflowed.

10. An apparatus for determining a time that a system'"'"'s main power was inactive comprising:

a system clock for providing a high-frequency clock signal when the system'"'"'s main power is active;

a low-frequency clock for providing a low-frequency clock signal independent of the activity of the system'"'"'s main power;

an LSB counter for accumulating transitions of the low-frequency clock signal while the system'"'"'s main power is inactive and for providing an LSB overflow signal when the LSB counter overflows, and for accumulating transitions of the high-frequency clock signal when the system'"'"'s main power is active;

an MSB counter for accumulating transitions of the LSB counter overflow signal when the system'"'"'s main power was inactive; and

a computational circuit for determining the time the system'"'"'s main power was inactive dependent on a number of LSB overflow signal transitions accumulated by the MSB counter when the system'"'"'s main power was inactive and a number of transitions of the high-frequency clock signal accumulated in the LSB counter when the system'"'"'s main power is active.

11. An apparatus in accordance with claim 10 wherein the computational means comprises means for determining the time the system'"'"'s main power was inactive by multiplying the number of LSB overflow signal transitions accumulated by the MSB counter when the system'"'"'s main power was inactive by a number of transitions of the high-frequency clock signal accumulated in the LSB counter when the system'"'"'s main power is active.

12. An apparatus in accordance with claim 11 wherein the LSB counter further comprises a logic circuit causing accumulation of transitions of the high-frequency clock signal dependent on an integer multiple number of periods of the LSB overflow signal when the system'"'"'s main power is active.

13. An apparatus in accordance with claim 12 wherein the MSB counter further comprises a circuit for preventing the accumulation of transitions of the LSB overflow signal when the MSB counter has overflowed.

14. An apparatus in accordance with claim 13 further comprising means for resetting the LSB counter after the time the system'"'"'s main power was inactive was determined.

15. A method of determining a time that a system'"'"'s main power was inactive comprising the steps of:

providing a clock signal while the system'"'"'s main power is inactive, wherein the clock signal has transitions;

accumulating the transitions of the clock signal while the system'"'"'s main power is inactive;

determining a periodicity of the clock signal after the system'"'"'s main power transitions active; and

determining the time the system'"'"'s main power was inactive dependent on a number of accumulated transitions of the clock signal when the system'"'"'s main power was inactive and the determined periodicity of the clock signal after the system'"'"'s main power transitions active.

16. A method in accordance with claim 15 wherein the step of providing comprises determining the time the system'"'"'s main power was inactive by multiplying the number of accumulated transitions of the clock signal when the system'"'"'s main power was inactive by the determined periodicity of the clock signal after the system'"'"'s main power transitions active.

17. A method in accordance with claim 15 wherein the step of determining a periodicity of the clock signal comprises determining the periodicity of the clock signal by determining an average periodicity dependent on more than one period of the clock signal.

18. A method in accordance with claim 15 wherein the step of determining comprises determining a periodicity of the clock signal using a high-frequency system clock signal available after the system'"'"'s main power transitions active.

19. A system for determining a key-off time of a vehicle, said system comprising:

keyswitch means for providing power when a to be provided key positions the keyswitch means in an active state, and for ceasing provision of power when the key positions the keyswitch means in an inactive state;

means for accumulating transitions of a clock signal when the power is not provided;

means for determining a periodicity of the clock signal after the power is provided; and

means for determining the time the system'"'"'s power was in the inactive state dependent on a number of accumulated transitions of the clock signal when the system'"'"'s power was the inactive state and the determined periodicity of the clock signal when the system'"'"'s power is in the active state.

20. A method of determining off-time of a system'"'"'s main power comprising the steps of:

providing a first clock signal from a first clock signal source, wherein a frequency accuracy of the first signal is relatively low;

providing a second clock signal from a second clock signal source, wherein the frequency accuracy of the second clock signal is higher than the accuracy of the first clock signal;

counting the first clock signal while the system'"'"'s main power is off to develop an off-time count indicative of the off-time of the system'"'"'s main power;

determining a period of the first clock signal dependent on the second clock signal when the system'"'"'s main power is on; and

determining the off-time of the system'"'"'s main power dependent on the determined period of the first clock signal and the off-time count.