Analyzing device for saving semiconductor memory failures

• US 5,410,687 A
• Filed: 12/01/1993
• Issued: 04/25/1995
• Est. Priority Date: 03/19/1990
• Status: Expired due to Term

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Okino, Noboru, Fujisaki, Kenichi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Snyder, Glenn
• Application Number:
  US08/159,704
• Time in Patent Office: 510 Days
• Field of Search: 371/10.3, 365/200
• US Class Current: 365/201
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test. When the former is greater than the latter, the column address is decided as a failing address line, is counted by a failing address line counter and is written into a failing address memory. The row address is sequentially changed, beginning with a 0, at each failing column address when a "1" is read out of the failure analysis memory. The contents of the memories are each rewritten by subtracting a 1 therefrom and the fail counter is decremented by one.

Claims

1. An analyzing device for saving memory failures, comprising:

address generating means for sequentially generating column and row addresses in pairs;

a failure analysis memory, sequentially supplied with the result of a logical comparison for each memory cell of a memory under test, for storing a data "1" at an address thereof specified by one of said column and row address pairs when said result of comparison is a signal representing a disagreement between data supplied to said memory under test and data read out therefrom, said failure analysis memory performing a read modify write operation, said memory under test having spare lines which are used as substitutes for address lines which are determined to be failing;

an inhibit gate, supplied with said data "1" read out of said failure analysis memory, as an inhibit signal, and said result of the comparison for inhibiting said result of comparison from passing therethrough when a "1" is read out of said failure analysis memory and supplied thereto during said read modify write operation of said failure analysis memory, thereby inhibiting from passing therethrough a second and subsequent disagreement signals detected from the same memory cell of said memory under test;

a column address fail count memory, supplied, as an address, with the same column address as supplied to said failure analysis memory simultaneously therewith, for performing a read modify write operation each time said disagreement signal is applied thereto as an enable signal from said inhibit gate;

first arithmetic means for adding a "1" to data read out of said column address fail count memory during said read-modify-write operation thereof and providing the result of said addition to said column address fail count memory to be written thereinto as a count value during said read modify write operation, whereby a count value stored at each address of said column address fail count memory is updated in accordance with the number of defective cells on the corresponding column address line of said memory under test;

a row address fail count memory, supplied, as an address, with the same row address as supplied to said failure analysis memory simultaneously therewith, for performing a read modify write operation each time said disagreement signal is applied thereto as an enable signal from said inhibit gate;

second arithmetic means for adding a "1" to data read out of said row address fail count memory during said read-modify-write operation thereof and providing the result of said addition to said row address fail count memory to be written thereinto as a count value during said read modify write operation, whereby a count value stored at each address of said row address fail count memory is updated in accordance with the number of defective cells on the corresponding row address line of said memory under test;

fail counting means for counting the number of said enable signals outputted from said inhibit gate; and

control means for controlling operations of said failure analysis memory, said column address fail count memory, said row address fail count memory and said fail counting means as well as operating said failure analysis memory, said column address fail count memory, said row address fail count memory and said fail counting means simultaneously during a read modify write mode for completing the counting operation of defective cells concurrently with the end of the test for said memory under test.

2. The device according to claim 1, further comprising:

spare line number register means for storing the numbers of usable row and column spare lines of said memory under test;

comparator means for comparing the number of defective cells sequentially read out of said column address fail count memory by application of said column address thereto from said address generating means with said number of row spare lines stored in said spare line number register means and outputting, when the former is greater than the latter, a column fail signal indicating that the column address line of said memory under test corresponding to said column address is defective, and for comparing the number of defective cells sequentially read out of said row address fail count memory by application of said row address thereto from said address generating means with said number of column spare lines stored in said spare line number register means and outputting, when the former is greater than the latter, a row fail signal indicating that the row address line of said memory under test corresponding to said row address is defective;

failing address line counter means which counts said column fail signal outputted from said comparator means and counts said row fail signal outputted from said comparator means; and

failing address memory means which is supplied, as an address, with the column fail signal count value of said failing address line counter means, for storing, each time said column fail signal is outputted from said comparator means, the column address at that time written as data, and which is supplied, as an address, with the row fail signal count value of said failing address line counter means, for storing, each time said row fail signal is outputted from said comparator means, the row address at that time as data.

3. The device according to claim 2, wherein said comparator means includes a first multiplexer for selecting either one of the number of defective cells read out of said column address fail count memory and the number of defective cells read out of said row address fail count memory for comparison with either one of the number of row or the number of column spare lines, and wherein said failing address memory means includes a second multiplexer for selecting either one of said column address or said row address in correspondence to the selection by said first multiplexer, whereby either one of said column address and said row address is written into said failing address memory means as data.

4. The device according to claim 1, wherein said fail counting means includes a total fail count memory which performs a read modify write operation each time said enable signal is applied thereto from said inhibit gate, and third arithmetic means for adding a "1" to data read out from said total fail count memory during said read modify write operation thereof and providing the result of said addition to said total fail count memory to be written thereinto during said read modify write operation.

5. The device according to claim 4, wherein said first, second and third arithmetic means are each an adder-subtractor which can be controlled to add a "1" to or subtract a "1" from input data in response to an operation control signal from said control means, and wherein said control means controls said address generating means and said failure analysis memory to read out said failure analysis memory by sequentially changing the row or column address thereof for a desired column or row address of said failure analysis memory and also controls said first, second and third arithmetic means to perform a subtractive operation, whereby, each time a "1" representing a defective cell on said desired column or row address of said failure analysis memory is read out therefrom, a "1" is subtracted from the numbers of column and row defective cells at the corresponding addresses of said column and row address fail count memories to update said input data.

6. The device according to claim 5, further comprising:

a multiplexer for selectively outputting either one of said number of column defective cells read out of said column address fail count memory and said number of row defective cells read out of said row address fail count memory; and

rewrite inhibit means for detecting whether said number of column or row defective cells selectively outputted from said multiplexer is a "0", and inhibiting, upon detection of a "0", said enable signal from being applied to said total fail count memory thereby inhibiting a rewrite of the contents of said total fail count memory.

7. The device according to claim 5, wherein each of said adder-subtractors includes:

an arithmetic logic unit provided with a first set of input terminals, the number of which is equal to that of bits of an input data thereto, a second set of input terminals, the number of which is equal to that of said first input terminals, and a set of output terminals, the number of which is equal to that of said first input terminals, said second set of input terminals being always supplied with "0s" except one input terminal thereof into which the least significant bit of an input data is inputted, said arithmetic and logic unit being capable of selectively performing an addition or subtraction of data inputted into said second input terminals to or from data inputted into said first input terminals;

all-zero detector means for outputting a "0" when detecting that all bits of said input data to said first input terminals are "0s", and outputting a "1" in other cases;

all-one detector means for outputting a "0" when detecting that all bits of said input data to said first input terminals are "1s", and outputs a "1" in other cases; and

selector means for selecting the output of said all-one detector means or all-zero detector means, depending on whether said arithmetic and logic unit is set for addition or subtraction, and applying said selected output to said least significant bit terminal of said second input terminals of said arithmetic and logic unit.

8. An analyzing device for saving memory failures, comprising:

address generating means for sequentially generating column and row addresses in pairs;

a failure analysis memory supplied with the result of a logical comparison for each memory cell of a memory under test specified by each of said column and row address pairs supplied thereto, for storing data "1" at an address thereof specified by one of said column and row address pairs when said result of the comparison is a signal representing a disagreement between data supplied to said memory under test and data read out therefrom, said memory under test having spare lines which are used as substitutes for address lines which are determined to be failing;

memory read out means for sequentially reading out the results of the logical comparison stored in said failure analysis memory by applying said column and row address pairs from said address generating means to said failure analysis memory after said failure analysis memory has stored all the results of the logical comparison;

a column address fail count memory, supplied, as an address, with the same column address as supplied to said failure analysis memory for read out thereof simultaneously therewith, for performing a read modify write operation each time a "1" read out of said failure analysis memory is applied thereto as an enable signal;

first arithmetic means for adding a "1" to data read out of said column address fail count memory during said read-modify-write operation thereof and providing the result of said addition to said column address fail count memory to be written thereinto as a count value during said read modify write operation, whereby a count value stored at each address of said column address fail count memory is updated in accordance with the number of defective cells on the corresponding column address line of said memory under test;

a row address fail count memory, supplied, as an address, with the same row address as supplied to said failure analysis memory for read out thereof simultaneously therewith, for performing a read modify write operation each time a "1" read out of said failure analysis memory is applied thereto as an enable signal;

second arithmetic means for adding a "1" to data read out from said row address fail count memory during said read-modify-write operation thereof and providing the result of said addition to said row address fail count memory to be written thereinto as a count value during said read modify write operation, whereby a count value stored at each address of said row address fail count memory is updated in accordance with the number of defective cells on the corresponding row address line of said memory under test;

fail counting means for counting the number of said enable signals read out from said failure analysis memory; and

control means for controlling operations of said failure analysis memory, said column address fail count memory, said row address fail count memory and said fail counting means as well as operating said column address fail count memory, said row address fail count memory and said fail counting means simultaneously in a read modify write mode so that the number of defective cells on the row address lines and the total number of defective cells can be counted at the same time by only one scanning of said failure analysis memory.

9. The device according to claim 8, further comprising:

spare line number register means for storing the numbers of usable row and column spare lines of said memory under test;

comparator means for comparing the number of defective cells sequentially read out of said column address fail count memory by application of said column address thereto from said address generating means with said number of row spare lines stored in said spare line number register means and outputting, when the former is greater than the latter, a column fail signal indicating that the column address line of said memory under test corresponding to said column address is defective, and for comparing the number of defective cells sequentially read out of said row address fail count memory by application of said row address thereto from said address generating means with said number of column spare lines stored in said spare line number register means and outputting, when the former is greater than the latter, a row fail signal indicating that the row address line of said memory under test corresponding to said row address is defective;

failing address line counter means which counts said column fail signal outputted from said comparator means and counts said row fail signal outputted from said comparator means; and

failing address memory means which is supplied, as an address, with the column fail signal count value of said failing address line counter means, for storing, each time said column fail signal is outputted from said comparator means, the column address at that time as data, and which is supplied, as an address, with the row fail signal count value of said failing address line counter means, for storing, each time said row fail signal is outputted from said comparator means, the row address at that time as data.

10. The device according to claim 9, wherein said comparator means includes a first multiplexer for selecting either one of the number of defective cells read out from said column address fail count memory and the number of defective cells read out from said row address fail count memory for comparison with either one of the number of row or the number of column spare lines, and wherein said failing address memory means includes a second multiplexer for selecting either one of said column address and said row address in correspondence to the selection by said first multiplexer whereby either one of said column address or said row address is written into said failing address memory means as data.

11. The device according to claim 8, wherein said fail counting means includes a total fail count memory which performs a read modify write operation each time a "1" read out of said failure analysis memory is applied thereto as an enable signal, and third arithmetic means for adding a "1" to data read out from said total fail count memory during said read modify write operation thereof and providing the result of said addition to said total fail count memory to be written thereinto by said read modify write operation.

12. The device according to claim 11, wherein said first, second and third arithmetic means are each an adder-subtractor which can be controlled to add a "1" to or subtract a "1" from input data in response to an operation control signal from said control means, and wherein said control means controls said address generating means and said failure analysis memory to read out said failure analysis memory by sequentially changing the row or column address thereof for a desired column or row address of said failure analysis memory and also controls said first, second and third arithmetic means to perform a subtractive operation, whereby, each time a "1" representing a defective cell on said desired column or row address of said failure analysis memory is read out therefrom, a "1" is subtracted from the respective numbers of column and row defective cells at the corresponding addresses of said column and row address fail count memories to update said input data.

13. The device according to claim 12, further including a multiplexer for selectively outputting either one of said number of column defective cells read out from said column address fail count memory and said number of row defective cells read out from said row address fail count memory, and rewrite inhibit means for detecting whether said number of column or row defective cells selectively outputted from said multiplexer is a "0" or not and inhibiting, upon detection of "0", said enable signal from being applied to said total fail count memory thereby inhibiting a rewrite of the contents of said total fail count memory.

14. The device according to claim 12, wherein each of said adder-subtractor includes:

an arithmetic and logic unit provided with a first set of input terminals the number of which is equal to the number of bits of an input data thereto, a second set of input terminals the number of which is equal to the number of said first input terminals, and a set of output terminals the number of which is equal to the number of said first input terminals, said second set of input terminals being always supplied with "0s" except one input terminal thereof into which a least significant bit is inputted, said arithmetic and logic unit being capable of selectively performing an addition or subtraction of a data inputted into said second input terminals to or from a data inputted into said first input terminal;

all-zero detector means which outputs a "0" when it detects that all bits of said input data to said first input terminals are "0", and outputs a "1" in other cases;

all-one detector means which outputs a "0" when it detects that all bits of said input data to said first input terminals are "1", and outputs a "1" in other cases; and

selector means which selects the output of one of said all-one detector means or said all-zero detector means, depending on whether said arithmetic and logic unit is set for addition or subtraction, and applies said selected output to said least significant bit terminal of said second input terminals of said arithmetic and logic unit.