Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems

• US 5,410,710 A
• Filed: 12/30/1993
• Issued: 04/25/1995
• Est. Priority Date: 12/21/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Papworth, Dave, Sarangdhar, Nitin V., Carson, David G., Nizar, P. K.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/176,136
• Time in Patent Office: 481 Days
• Field of Search: 395/725, 395/325, 395/275, 371/68.3, 371/25.1, 340/825.51, 340/825.5, 370/85.6
• US Class Current: 710/266
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two data wires for 2-bit parallel-serial data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to the lowest priority mode arbitration procedure also provides for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus.

Claims

1. A multiprocessor programmable interrupt controller system for operation in a multiprocessor system having a common system bus, at least one I/O peripheral subsystem with a set of interrupt request signal lines, and at least two processor units, one processor unit being a functional redundancy checking (FRC) unit having a master processor and a checker processor operating with common core and CPU bus clocks, the multiprocessor programmable interrupt controller system comprising:

a) an interrupt bus synchronizing clock signal with a rate that is less than one half the common core clock rate;

b) a synchronous interrupt bus for transmitting the interrupt bus synchronizing clock signal, for interrupt request data communication, and for arbitration messages for control of the interrupt bus;

c) an interrupt delivery unit (IDU) connected to the interrupt bus comprising;

i) a set of interrupt request signal input pins for accepting interrupt request signals from a set of I/O peripheral interrupt request lines, an interrupt request signal indicated by activating a corresponding input pin,

ii) a redirection table, coupled to the interrupt request signal input lines, for selecting an interrupt request message corresponding to the active input lines, the interrupt request message comprising an interrupt vector containing interrupt priority level, servicing mode, and processor selection information,

iii) means, coupled to the redirection table and to the interrupt bus, for broadcasting the redirection table interrupt message on the interrupt bus, and

iv) means, coupled to the interrupt bus, for arbitrating for control of the interrupt bus; and

d) an interrupt acceptance unit (IAU) connected to the interrupt bus and to an associated processor unit comprising;

i) means for receiving interrupt request messages that have been broadcast on the interrupt bus,

ii) means for accepting interrupt requests for which the associated processor is eligible to service,

iii) means for pending accepted interrupt request messages until the associated processor is available to service the interrupt request,

iv) means for broadcasting interrupt request messages from its associated processor unit on the interrupt bus,

v) means for arbitrating control of the interrupt bus connected to the interrupt bus,

vi) means for lowest priority mode arbitration on the interrupt bus between IAUs eligible to service a given interrupt request, wherein an IAU associated with an eligible processor operating on a task of lowest priority relative to all other eligible processors is selected to service the given interrupt request, and

vii) means for synchronizing IAU-accepted interrupt request messages with the associated processor core clock.

2. The controller of claim 1 wherein the synchronous interrupt bus comprises three wires, one wire for transmitting the interrupt bus synchronizing clock signal, a first and second data wire for interrupt request communication, the first data wire also used for single-wire arbitration messages.

3. The controller system of claim 2 wherein the IDU means and the IAU means for interrupt bus arbitration are each logically-OR connected to the interrupt bus for arbitration of the control of the interrupt bus, each IAU and IDU having a preassigned unique, fixed length, binary coded arbitration identification number assigned from a set of N integers, where N is the total number of IDUs and IAUs, hereinafter referred to as agents, the agents using a method of arbitration comprising the following steps:

a) each agent desiring control of the interrupt bus at a given instant of time arbitrates, by serially driving the first data wire with its arbitration identification number, one bit per bus cycle in descending order of bit significance;

b) each agent of step (a) monitoring the first data wire during each interrupt bus cycle of the arbitration procedure so that, if the first data wire is in a logically asserted state in any given arbitration cycle when its corresponding bit of its arbitration identification is not logically asserted, a non-asserting agent loses and drops out of the arbitration; and

c) repeating steps (a) and (b) until all bits of the arbitration identification number have been exhausted so that an agent remaining after the last bit is applied wins the arbitration and control of the interrupt bus.

4. The controller system of claim 3 wherein the arbitration is followed by a procedure for adjusting the arbitration identification numbers of each agent in order to distribute assignment of interrupt request assignment amongst all eligible processors, the adjusting procedure comprising the following steps:

a) the winning agent is assigned an arbitration identification number of zero;

b) incrementing by one the arbitration identification number of all other agents except the agent with arbitration identification number N-1; and

c) assigning the arbitration identification of the winning agent to the agent with arbitration identification of N-1.

5. The controller system of claim 3 wherein the agents are electrically open-drain connected to the interrupt bus for reduced loading on the interrupt bus when not driven by an agent.

6. The controller system of claim 2 wherein the means for lowest priority mode arbitration for finding an eligible processor with the current lowest priority task further comprises means for:

a) assigning to each IAU a lowest priority task number corresponding to each IAU associated processor a current processor task priority;

b) forming a logical complement of each lowest priority task number;

c) each eligible IAU sequentially driving the first data wire with its complemented lowest priority task number beginning with its most significant bit in descending bit order, one bit at a time for each interrupt bus clock cycle;

d) each eligible IAU monitoring the first data wire for each interrupt bus clock cycle so that, if the first data wire is logically asserted when a given IAUs corresponding bit is not asserted, the given IAU drops out of the lowest priority mode arbitration and all other eligible processors continue arbitration; and

e) repeating steps (c) and (d) until all bits of the complemented lowest priority task number has been used and a single IAU remains, the remaining IAU being the lowest priority mode arbitration winner.

7. The controller system of claim 6 further comprising means for appending to each IAU lowest priority task number, each IAU'"'"'s arbitration identification number as a field of lower order bits for the purpose of selecting a lowest priority mode winner when more than one eligible processor'"'"'s task is of equal lowest priority.

8. The controller system of claim 1 wherein the IAU further comprises remote read means for an IAU to request reading the contents of a register with a preassigned address in a target IAU, each IAU having a preassigned binary coded identification number, each of the remote read means comprising means for:

a) selecting a physical destination mode of interrupt bus message delivery;

b) specifying the target IAU identification number as the address of the destination;

c) placing a number corresponding to the address of the register whose contents are to be read and causing the target IAU to place the contents of the addressed register on the interrupt bus; and

d) reading of the register contents on the interrupt bus by the IAU requesting the remote IAU register read.

9. The controller system of claim 1 wherein the IAU is associated with the master CPU and further comprises a second IAU associated with, and coupled to, the checker CPU for bidirectional transfer of interrupt-related messages, and unidirectionally coupled to the interrupt bus solely for receiving messages broadcast on the interrupt bus.

10. The controller system of claim 1 further comprising a clock generator coupled to the FRC unit, for generating FRC CPU bus and core clock signals, each FRC CPU bus and clock signals being an integer harmonic of the interrupt bus synchronizing clock signal.

11. The controller system of claim 10 wherein the clock generator further comprises means for generating an interrupt bus synchronizing clock signal, coupled to the interrupt bus for transmitting the interrupt bus synchronizing clock signal.

12. The controller system of claim 1 wherein the IAU synchronizing means comprises means for synchronizing IAU-accepted interrupted request messages with the associated processor CPU bus clock.

13. The controller system of claim 1 wherein the IAU synchronizing means comprises a first stage synchronizer and second stage synchronizer, the first stage synchronizer for synchronizing IAU-accepted interrupt request messages with the associated processor CPU bus clock, and the second stage synchronizer for synchronizing the first stage synchronizer output with the associated processor core clock.

14. The controller system of claim 13 wherein the second stage synchronizing means further comprises:

a) gate means for gating the fast stage synchronizing means output; and

b) a state machine for generating a gate control signal for controlling the gate means output on and off, turning the gate output on for a prescribed interval whenever the first stage synchronizer output transitions from low to high and a low to high transition of the associated core clock occurs within a core clock period interval of the first stage synchronizer output low to high transition.

15. The controller system of claim 14 wherein the prescribed gate on interval is at least one core clock period.