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Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems

  • US 5,410,710 A
  • Filed: 12/30/1993
  • Issued: 04/25/1995
  • Est. Priority Date: 12/21/1990
  • Status: Expired due to Term
First Claim
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1. A multiprocessor programmable interrupt controller system for operation in a multiprocessor system having a common system bus, at least one I/O peripheral subsystem with a set of interrupt request signal lines, and at least two processor units, one processor unit being a functional redundancy checking (FRC) unit having a master processor and a checker processor operating with common core and CPU bus clocks, the multiprocessor programmable interrupt controller system comprising:

  • a) an interrupt bus synchronizing clock signal with a rate that is less than one half the common core clock rate;

    b) a synchronous interrupt bus for transmitting the interrupt bus synchronizing clock signal, for interrupt request data communication, and for arbitration messages for control of the interrupt bus;

    c) an interrupt delivery unit (IDU) connected to the interrupt bus comprising;

    i) a set of interrupt request signal input pins for accepting interrupt request signals from a set of I/O peripheral interrupt request lines, an interrupt request signal indicated by activating a corresponding input pin,ii) a redirection table, coupled to the interrupt request signal input lines, for selecting an interrupt request message corresponding to the active input lines, the interrupt request message comprising an interrupt vector containing interrupt priority level, servicing mode, and processor selection information,iii) means, coupled to the redirection table and to the interrupt bus, for broadcasting the redirection table interrupt message on the interrupt bus, andiv) means, coupled to the interrupt bus, for arbitrating for control of the interrupt bus; and

    d) an interrupt acceptance unit (IAU) connected to the interrupt bus and to an associated processor unit comprising;

    i) means for receiving interrupt request messages that have been broadcast on the interrupt bus,ii) means for accepting interrupt requests for which the associated processor is eligible to service,iii) means for pending accepted interrupt request messages until the associated processor is available to service the interrupt request,iv) means for broadcasting interrupt request messages from its associated processor unit on the interrupt bus,v) means for arbitrating control of the interrupt bus connected to the interrupt bus,vi) means for lowest priority mode arbitration on the interrupt bus between IAUs eligible to service a given interrupt request, wherein an IAU associated with an eligible processor operating on a task of lowest priority relative to all other eligible processors is selected to service the given interrupt request, andvii) means for synchronizing IAU-accepted interrupt request messages with the associated processor core clock.

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