Input/output system for a massively parallel, single instruction, multiple data (SIMD) computer providing for the simultaneous transfer of data between a host computer input/output system and all SIMD memory devices

• US 5,410,727 A
• Filed: 11/22/1993
• Issued: 04/25/1995
• Est. Priority Date: 10/24/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kienzle, Margaret M. L., Li, Hungwen, Sheng, Ming-Cheng, Jaffe, Robert S.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Donoghue, L.
• Application Number:
  US08/157,232
• Time in Patent Office: 519 Days
• Field of Search: 395/800, 395/375, 395/275, 395/425, 395/200
• US Class Current: 709/234
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 7/785 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Abstract

A two-dimensional input/output system for a massively parallel SIMD computer system providing an interface for the two-way transfer of data between a host computer and the SIMD computer. A plurality of buffers equal in number, and distributed with the individual processing elements of the SIMD computer are used to provide a temporary storage area which allows data in different formats to be mapped in a format suitable for transfer to the host computer or for transfer to the SIMD processing elements. The temporary storage is controlled in such a way as to transfer entire blocks of data in a single SIMD system clock cycle thereby achieving an input/output data rate of N bits/cycle for a SIMD computer consisting of N processors. The system is capable of handling irregular as well as regular data structures. The system also emphasizes a distributed approach in having the input/output system divided into N pieces and distributed to each processor to reduce the wiring complexity while maintaining the I/O rate.

Claims

1. An input/output (I/O) system for a massively parallel, single instruction, multiple data (SIMD) computer providing bi-directional, two-dimensional data transfer between a host computer and said SIMD computer, wherein the data transfer is two-dimensional because data comprising N words each word up to n-bits in length is simultaneously transferred one N-bit plane at a time between the host computer I/O system and all SIMD memory devices of the SIMD computer, said SIMD computer comprising a parallel array processor comprising N a parallel linked processors, with each processor being coupled to an associated one of N SIMD memory devices, each of said N SIMD memory devices organized as D memory planes each comprising N bits, said input/output system comprising:

(a) a temporary storage means coupled between said host computer and said N SIMD memory devices for the bi-directional, two-dimensional transfer of data between said host computer and said SIMD computer, wherein said temporary storage means includes N corner turning buffers, each one of said plurality of corner turning buffers being coupled with one of said N SIMD memory devices;

(b) an input/output processing means, controlled by a system clock which generates clock cycles, for controlling the flow of data between said host computer and said N corner turning buffers, and for controlling the flow of data between said N corner turning buffers and said N SIMD memory devices, said input/output processing means distributing the N words of up to n-bits length each of data from the host computer to said N corner turning buffers and arranging said data therein as n memory planes each comprising N bits therein, each of said n memory planes corresponding to an associated one of said D memory planes of said SIMD memory, and further distributing said N words of up to n-bits length each to said corresponding SIMD memory devices of the SIMD computer one N-bit plane at a time in a single system clock cycle.

2. The input/output system of claim 1 wherein said temporary storage means includes a control circuit means for providing timing and selection signals for the transfer of data between said host computer and said N corner turning buffers and for the transfer of data between said N corner turning buffers and said SIMD memory devices.

3. An input/output (I/O) system for a massively parallel, single instruction, multiple data (SIMD) computer providing two-dimensional data transfer between a host computer and said SIMD computer, wherein the data transfer is two-dimensional because data comprising N words each word up to n-bits in length is simultaneously transferred one N-bit plane at a time between the host computer I/O system and all SIMD memory devices of the SIMD computer, said SIMD computer having a parallel array processor comprising N parallel linked processors, with each processor being coupled to an associated one of N SIMD memory devices, each of said N SIMD memory devices organized as D memory planes each comprising N bits, said input/output system comprising:

(a) an input/output channel for the transfer of data between said SIMD computer and said host computer;

(b) a temporary storage means connected between said input/output channel and said N SIMD memory devices for the bi-directional, two-dimensional transfer of data between said host computer and said SIMD computer said temporary storage means comprising;

(i) N corner turning buffers, each one of said N corner turning buffers being coupled with one of said N SIMD memory devices, and

(ii) a control circuit means for providing timing and selection signals for the transfer of data between said host computer and said N corner turning buffers and for the transfer of data between said N corner turning buffers and said N SIMD memory devices; and

(c) an input/output processing means, controlled by a system clock which generates clock cycles, for controlling the flow of data between said host computer and said N corner turning buffers, and for controlling the flow of data between said N corner turning buffers and said N SIMD memory devices,

said input/output processing means distributing the N words of up to n-bits length each of data from said host computer to said N corner turning buffers and arranging said data therein as n memory planes each comprising N bits therein, each of said n memory planes corresponding to an associated one of said D memory planes of said SIMD memory, and further distributing N words of up to n-bits length each to said corresponding SIMD memory devices of the SIMD computer one N-bit plane at a time in a single system clock cycle.

4. The input/output system of claim 3 wherein said input/output channel is a n-bit bi-directional data bus that interconnects said host computer and said input/output processing means, said host computer and said temporary storage means, and said host computer and an array control unit.

5. The input/output system of claim 3 wherein each of said plurality of N corner turning buffers is a 32-bit buffer.

6. The input/output system of claim 3 wherein each of said plurality of N corner turning buffers is independently addressable by said input/output processing means.

7. The input/output system of claim 6 wherein said N corner turning buffers are addressable by the host computer or the input/output processing means as N addressable words each having n bits.

8. The input/output system of claim 3 wherein said N corner turning buffers are addressable by the SIMD array of processors as n addressable words each having N bits.

9. The input/output system of claim 3 wherein said N corner turning buffers are addressable by said host computer as n-bit words distributed over M segments of contiguous buffers wherein a total of M Segment starting addresses and M segment lengths are generated by said input/output processing means to accommodate the transfer of a continuous block of data from said host computer to said buffers, and the sum of the segment lengths is less than or equal to N.

10. The input/output system of claim 3 wherein said control circuit means comprises address decoding means for generating a N corner turning enable signals for the transfer of data to a predetermined number of said plurality of buffers.

11. The input/output system of claim 10 where said control circuit means further includes:

multiplexer means for determining which one of n locations of the predetermined number of N corner turning buffers from which data is to be transferred to associated SIMD memory devices in a single clock cycle; and

demultiplexer means for determining which one of n locations of the predetermined number of N corner turning buffers to which data is to be transferred from associated SIMD memory devices.

12. The input/output system of claim 10 wherein said address decoding means generates said plurality of enable signals from a buffer identification code and a data type code received from said input/output processing means.

13. The input/output system of claim 11 wherein said control circuit means further includes:

counter means which provides control signals for controlling said multiplexer means and said demultiplexer means; and

comparator means for determining the top count for said counter means.

14. The input/output system of claim 13 wherein said comparator means compares the count of said counter with said word length and upon a match provides a stop signal to said counter.

15. The input/output system of claim 13 wherein said counter means comprises one 5-bit counter, said counters provide selection control for said multiplexers and said demultiplexers.

16. The input/output system of claim 15 wherein said counter receives said data type code from said input/output processing means and decodes said data type code as the length of the word and stores the length into said comparator means.

17. The input/output system of claim 11 wherein said multiplexer means comprises N 32-to-1 multiplexers, each of said N 32-to-1 multiplexers corresponding to an associated corner turning buffer;

said N 32-to-1 multiplexers providing N bits of data from an n memory plane to an associated D memory plane of said N SIMD memory devices in a single clock cycle.

18. The input/output system of claim 17 wherein said demultiplexer means comprises N 1-to-32 demultiplexers, said demultiplexers providing N bits of data from one D memory plane of said N SIMD memory devices to an associated n memory plane of said N corner turning buffers in a single clock cycle.

19. The two-dimensional input/output system of claim 3 wherein said input/output processing means comprises:

(a) an address generation unit for generating the address for a particular buffer of said plurality of buffers and for generating the address for a particular memory device from said plurality of SIMD memory devices; and

(b) a microprocessor and associated memory for generating all control signals for said flow of data.

20. The input/output system of claim 19 wherein said address generation unit comprises an address queue which provides a string of buffer addresses that are sequentially followed.

21. The input/output system of claim 20 wherein said microprocessor and associated memory contain the input/output program which generates said plurality of control signals.

22. The input/output system of claim 21 wherein said input/output processing means further comprises a program which prepares data for transfer from said host computer to said plurality of buffers when data length is greater than the number of said plurality of buffers.

23. A single instruction multiple data (SIMD) processor comprising:

(a) a parallel array processor comprising N parallel linked processors, with each being coupled to an associated one of N SIMD memory devices;

(b) an array control unit for controlling said N parallel linked processors; and

(c) an input/output system, controlled by a system clock which generates clock cycles, for said single instruction multiple data processor providing two-dimensional data transfer between a host computer and said plurality of parallel linked processors, wherein the data transfer is two-dimensional because data comprising N words each word up to n-bits in length is simultaneously transferred one N-bit plane at a time between the host computer I/O system and all SIMD memory devices of the SIMD computer, said input/output system comprising;

(i) an input/output channel for the transfer of data between said SIMD computer and said host computer;

(ii) a temporary storage means connected between said input/output channel and said N SIMD memory devices for the bi-directional, two-dimensional transfer of data between said host computer and said SIMD computer, said temporary storage means comprising N corner turning buffers each one of said N corner turning buffers being directly coupled with one of said [plurality of said N SIMD memory devices, and a control circuit means for providing timing and selection signals for the transfer of data between said host computer and said N corner turning buffers and also between said N corner turning buffers and said N SIMD memory devices; and

(iii) an input/output processing means, controlled by a system clock which generates clock cycles, for controlling the flow of data between said host computer and said N corner turning buffers, and for controlling the flow of data between said N corner turning buffers and said N SIMD memory devices.

24. The single instruction multiple data processor of claim 23 wherein said input/output channel is a n-bit bi-directional data bus that interconnects said host computer and said input/output processing means, said host computer and said N corner turning buffers, and said host computer and an array control unit.

25. The single instruction multiple data processor of claim 24 wherein each of said N corner turning buffers is independently addressable by said input/output processing means.

26. The single instruction multiple data processor of claim 25 wherein said N corner turning buffers are addressable by the SIMD array of processors as n addressable words each having N bits.

27. The single instruction multiple data processor of claim 25 wherein said N corner turning buffers are addressable by the host computer or the input/output processing means as N addressable words each having n bits.

28. The single instruction multiple data processor of claim 27 wherein said N corner turning buffers is addressable by said host computer as n-bit words distributed over M contiguous buffers wherein a total of M segment starting addresses and M segment lengths are generated by said input/output processing means to accommodate the transfer of a continuous block of data from said host computer to said buffers, and the sum of the segment lengths is less than or equal to N.

29. The single instruction multiple data processor of claim 28 wherein said control circuit means comprises an address decoding means for generating a plurality of enable signals for the transfer of data to a predetermined number of said plurality of buffers.

30. The single instruction multiple data processor of claim 29 wherein said control circuit means further comprises:

multiplexer means for determining which one of n locations of the predetermined number of N corner turning buffers from which data is to be transferred to associated SIMD memory devices in a single clock cycle; and

demultiplexer means for determining which one of n locations of the predetermined number of N corner turning buffers to which data is to be transferred from associated SIMD memory devices.

31. The single instruction multiple data processor of claim 30 wherein said control circuit means further comprises:

(a) counter means which provides control signals for controlling said multiplexer means and said demultiplexer means; and

(b) comparator means for determining the top count for said counter means.

32. The single instruction multiple data processor of claim 23 wherein said input/output processing means comprises:

(a) an address generation unit for generating the address for a particular buffer of said plurality of buffers and for generating the address for a particular memory device from said plurality of SIMD memory devices; and

(b) a microprocessor and associated memory for generating all control signals for said flow of data.

33. The single instruction multiple data processor of claim 32 wherein said address generation unit comprises an address queue which provides a string of buffer address'"'"' that are sequentially followed.

34. The single instruction multiple data processor of claim 33 wherein said microprocessor and associated memory contain the input/output program which generates said plurality of control signals.

35. The single instruction multiple data processor of claim 34 wherein said input/output processing means further comprises a program which prepares data for transfer from said host computer to said plurality of buffers when data length is greater than the number of said plurality of buffers.

36. A single instruction multiple data (SIMD) processor comprising:

(a) a parallel array processor comprising parallel linked processors, with each processor being coupled to an associated one of N SIMD memory devices;

(b) an array control unit for controlling said N parallel linked processors; and

(c) an input/output (I/O) system for said single instruction multiple data processor providing two-dimensional data transfer between a host computer and said plurality of N parallel linked processors wherein the data transfer is two-dimensional because data comprising N words each word up to n-bits in length is simultaneously transferred one N-bit plane at a time between the host computer I/O system and all SIMD memory devices of the SIMD computer, said input/output system comprising;

(i) a temporary storage means coupled between said host computer and said N SIMD memory devices for the bi-directional, two-dimensional transfer of data between said host computer and said SIMD computer, wherein said temporary storage means includes N corner turning buffers, each one of said N corner turning buffers being coupled with one of said N SIMD memory devices; and

(ii) an input/output processing means, controlled by a system clock which generates clock cycles, for controlling the flow of data between said host computer and said N corner turning buffers, and for controlling the flow of data between said N corner turning buffers and said N SIMD memory devices.

37. A single instruction multiple data processor of claim 36 wherein said temporary storage means includes a plurality of buffers, each one of said plurality of buffers being coupled with one of said plurality of SIMD memory devices.

38. A single instruction multiple data processor of claim 37 wherein said temporary storage means includes a control circuit means for providing timing and selection signals for the transfer of data between said host computer and said temporary storage means and for the transfer of data between said temporary storage means and said SIMD memory devices.

39. A method for providing bi-directional, two-dimensional inputting and outputting of data between a host computer and a massively parallel, single instruction, multiple data (SIMD) computer having a parallel array processor comprising N parallel linked processors with each processor being coupled to an associated one of N SIMD memory devices, said method comprising the steps of:

(a) when inputting data to said SIMD computer, first transferring data under the control of a system clock which generates clock cycles, between said host computer and a temporary storage means of said SIMD computer, said temporary storage means including N corner turning buffers, each one of said N corner turning buffers being coupled with one of said N SIMD memory devices, wherein each said data transfer is a two-dimensional transfer in a single system clock cycle because data comprising N words each word up to n-bits in length is simultaneously distributed one N-bit plane at a time between the host computer and all N corner turning buffers of the SIMD computer and arranged therein as n memory planes each comprising N bits; and

further

(b) transferring N words of up to n-bits each between said temporary storage means and said plurality of N SIMD memory devices one N-bit plane at a time in each system clock cycle; and

(c) when outputting data to said host computer from said SIMD computer, first transferring N words of up to n-bits each between said plurality of SIMD memory devices and said N corner turning buffers of said temporary storage means one N-bit plane at a time in each system clock cycle; and

further

(d) distributing data from said N corner turning buffers to a predetermined area of host computer memory in each system clock cycle.

40. The method of claim 39 wherein the step of distributing data from said host computer further includes the steps of:

(a) generating a plurality of enable signals for the transfer of data to a predetermined number of said N corner turning buffers; and

(b) transferring the data from said host computer to M segments of contiguous buffers of said N corner turning buffers addressable as n-bit words having N addresses, where N equals the number of said plurality of buffers and n is equal to the width of an individual buffer of said plurality of buffers.

41. The method according to claim 39 wherein the step of transferring data between said temporary storage means and a plurality of SIMD memory devices comprises the steps of:

(a) distributing data from said N corner turning buffers over a plurality of planes which comprise said plurality of SIMD memory devices in a first single system clock cycle, wherein each of said plurality of planes comprises a distribution of data in a two dimensional pattern for the simultaneous transfer of data to and from all SIMD memory devices of the SIMD computer; and

(b) distributing data from said plurality of planes over a plurality of n corner turning buffers which comprise said temporary storage means in a second single system clock cycle.

42. The method according to claim 41 wherein the step of distributing data from said plurality of planes further includes the steps of:

(a) determining by means of a demultiplexer which one of n locations of said plurality of buffers to which data is to be transferred from said plurality of planes; and

(b) transferring the data from said plurality of planes to M segments of contiguous buffers of said plurality of buffers addressable as n bit words having N addresses, where N equals the number of said plurality of buffers and n is equal to the width of an individual buffer of said plurality of buffers.

43. The method according to claim 42 wherein said step of determining the m locations includes the step of generating a set of control signals for controlling said demultiplexer.

44. The method according to claim 41 wherein the step of distributing data from said temporary storage means further includes the steps of:

(a) determining by means of a multiplexer which one of n locations of said N corner turning buffers from which data is to be transferred to said SIMD memory devices; and

(b) transferring the data from said temporary storage means to said plurality of planes addressable as N-bit words having n addresses, where N equals the number of said plurality of buffers and n is equal to the width of an individual buffer of said plurality of buffers.

45. The method according to claim 44 wherein said step of determining the n locations includes the step of generating a set of control signals for controlling said multiplexers.