Method for making an improved high voltage thin film transistor having a linear doping profile

• US 5,412,241 A
• Filed: 08/03/1993
• Issued: 05/02/1995
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L.
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US08/101,164
• Time in Patent Office: 637 Days
• Field of Search: 257/409, 257/347, 257/367, 257/488
• US Class Current: 257/409
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/861 Diodes

Abstract

This application is directed to an improved thin film SOI device in which a gate region extends over a thin layer of silicon having a lateral linear doping region on a buried oxide layer. The gate region of this invention includes a gate electrode and a field plate extending laterally from the gate electrode over the lateral linear doping region.

Claims

1. In a thin film SOI device comprising a buried oxide layer, a thin layer of silicon having a lateral linear doping region on said buried oxide layer, a top oxide layer on said thin layer of silicon, a gate region at one end of said thin layer, a drain region at an opposite end of said thin layer, a source region laterally separated from said gate region, the improvement comprising said gate region including a gate electrode and a field plate extending laterally from said gate electrode over said lateral linear doping region, wherein said buried oxide layer and said top oxide layer have the same thickness.

2. A thin layer SOI device as claimed in claim 1, wherein said linear lateral doping region depletes into both said buried oxide layer and said top oxide layer, thereby doubling the conductive charge placed on said lateral linear doping region.

3. A thin layer SOI device as claimed in claim 1, wherein said buried oxide layer and said top oxide layer each have a thickness ranging from about 1 to 1.5 microns.

4. A thin layer SOI device as claimed in claim 1, wherein said thin layer of silicon has a thickness ranging from 1000 to 2000 angstroms.

5. A thin layer SOI device as claimed in claim 1, wherein said gate electrode and said field plate each have a thickness of about 5000 angstroms.

6. A thin layer SOI device as claimed in claim 1, wherein said SOI device has a high breakdown voltage, such as approximately 710 volts.