Error reduction in switched capacitor digital-to-analog converter systems by balanced sampling

• US 5,412,387 A
• Filed: 04/06/1993
• Issued: 05/02/1995
• Est. Priority Date: 04/06/1993
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Vincelette, Scott, Ferguson, Paul F. Jr., Adams, Robert W.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/044,370
• Time in Patent Office: 756 Days
• Field of Search: 341/110, 341/122, 341/123, 341/143, 341/150, 341/172
• US Class Current: 341/150
• CPC Class Codes: H03M 3/324 characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004

Abstract

A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.

Claims

1. A DAC system comprising:

a first DAC connected and operable to sample a reference source, which provides a reference, at a first rate;

a second DAC connected and operable to sample the reference source at a second rate, the second rate being greater than the first rate; and

at least one load circuit connected and operable to sample the reference source at a third rate such that the level of the reference provided by the reference source is substantially the same each time a sample is taken.

2. A DAC system as claimed in claim 1 wherein the first and second DACs include first and second switched-capacitor filters, respectively, the first filter sampling the reference source at the first rate and the second filter sampling the reference source at the second rate.

3. A DAC system as claimed in claim 2 wherein the first and second DACs further include first and second sigma-delta DACs, respectivley.

4. A DAC system as claimed in claim 3 wherein the first and second DACs are coupled to a common reference clock and are synchronously operated, and the load circuit samples the reference source when the second DAC is sampling and the first DAC is not sampling.

5. A DAC system as claimed in claim 4 wherein the load circuit includes a network of capacitors and switches coupled to the reference source.

6. A DAC system as claimed in claim 5 wherein the load circuit further includes digital control logic, coupled to the network, to control the sampling by the load circuit.

7. A DAC system as claimed in either one of claims 1 or 6 wherein the second DAC further includes a variable rate interpolator increasing an interpolation ratio thereof upon a decrease in an input sampling frequency.

8. A DAC system comprising:

a first means for sampling a reference source, which provides a reference, at a first rate;

a second means for sampling the reference source at a second rate, the second rate being greater than the first rate; and

at least one circuit load means for sampling the reference source at a third rate such that the reference is at substantially the same level each time a sample is taken.

9. A DAC system as claimed in claim 8 wherein the first and second means for sampling include first and second switched-capacitor filters, respectively, the first filter sampling the reference source at the first rate and the second filter sampling the reference source at the second rate.

10. A DAC system as claimed in claim 9 wherein the first and second means for sampling further include first and second sigma-delta DACs, respectively.

11. A DAC system as claimed in claim 10 wherein the first and second means for filtering are coupled to a common clock source and are synchronously operated, and the at least one circuit load means samples the reference source when the second means for sampling is sampling and the first means for sampling is not sampling.

12. A DAC system as claimed in claim 11 wherein the at least one circuit load means includes a network of capacitors and switches coupled to the reference source.

13. A DAC system as claimed in claim 12 wherein the at least one circuit load means further includes digital control logic, coupled to the network, to control the sampling by the at least one circuit load means.

14. A DAC system as claimed in either of claims 8 or 13 wherein the second means for sampling further includes a variable rate interpolator increasing an interpolation ratio thereof upon a decrease in an input sampling frequency.

15. A method for equating reference source sampling by first and second devices which each periodically sample the reference source, which produces a reference, comprising the steps of:

with the first device, sampling the reference source at a first rate;

with the second device, sampling the reference source at a second rate; and

sampling the reference source at a third rate such that the level of the refence is substantially the same each time a sample is taken.