Driver circuit for shutters of a flat panel display

• US 5,412,396 A
• Filed: 11/09/1993
• Issued: 05/02/1995
• Est. Priority Date: 04/16/1993
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Bell Communications Research, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Nelson, Terence J.
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): CHIN, VIVIAN C
• Application Number:
  US08/149,263
• Time in Patent Office: 539 Days
• Field of Search: 345/89, 345/102, 345/148, 345/98, 345/87, 345/70, 377/107
• US Class Current: 345/89
• CPC Class Codes: G09G 2310/024 Scrolling of light from the illumination source over the display in combination with the scanning of the display screen
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/342 using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

A flat-panel display device 500, 600 with an active array of parallel longitudinal row backlights 520, 620 disposed in a first plane is disclosed. The row backlights sequentially emit a row of light for a fixed-duration row-interval of time t in successive row periods of duration p. Each row is illuminated once in each frame. The flat panel display device also has an array of longitudinal parallel liquid-crystal column shutters 531, 631 disposed in a second plane parallel to the first plane. The column shutters are oriented orthogonally to the row backlights so as to define pixels at each intersection of a column shutter and a row backlight. A driver 590, 690 is provided for causing the column shutters to make, at most, one transition from the "off" state to the "on" state or vice-versa every row period.

Claims

1. A display producing gray-scale images by means of data lines responsive to pulse-width modulation and driven by a circuit that comprises a shift register having one cell for each data input of the display, each cell comprising:

a memory for periodically receiving and storing an m+1 bit number D_m D_m-1 . . . D₀, the m^th bit D_m is the most significant bit and wherein the 0^th bit D₀ is the least significant bit, said memory comprising a plurality of flip-flops each for storing a bit of said m+1 bit number,

means for receiving m+1 delay signals which each correspond to one of said m+1 bits and applying said delay signals to a clear input of corresponding ones of said flip-flops, the delay signal associated with each bit having twice the period of the delay signal associated with a preceding bit, said delay signals setting each bit to logic zero, one at a time from the m^th bit to the 0^th bit, after a delay equal to one half the period of the delay signal corresponding to the bit,

an OR circuit connected to an output of each of said flip-flops and to the output of the preceding OR circuit, said output of each OR circuit also being connected to said clear input of the succeeding flip-flop except for the OR circuit corresponding to the D₀ bit, and

a cell output for driving said associated shutter with a voltage depending, at any time, on whether said m+1 bit number stored in said memory is zero or non-zero, said cell output being the output of said OR circuit corresponding to the D₀ bit.

2. A circuit for producing digitally controlled pulse-width modulated outputs from the stages of a shift register, each stage comprising

a memory for periodically receiving and storing an m+1 bit number D_m D_m-1 . . . D₀, where the m^th bit D_m is the most significant bit and wherein the 0^th bit D₀ is the least significant bit, said memory comprising a series of memory elements each for storing a bit of said m+1 bit number,

means for receiving m+1 delay signals which each correspond to one of said m+1 bits and applying said m+1 delay signals to clear inputs of corresponding ones of said memory elements, the delay signals associated with each bit having twice the frequency of the delay signal associated with a preceding bit, said means for receiving and applying said delay signals resetting each bit which is a logic one to logic zero, one bit at a time from the m^th to the 0^th bit, after a delay equal to one half the period of the delay signal corresponding to the bit,

OR circuit means comprising series connected OR circuits, the output of the last of said series connected OR circuits being the output of said stage, said OR circuits connecting the output of each memory element to the clear input of the succeeding memory element and to said output of said stage for producing said pulse-width modulated outputs, and

means for providing an enable signal as an input to the clear input of the memory element for the most significant bit and to the first of said series connected OR circuits.