Data processing apparatus dual-bus data processing with reduced cpu and memory requirements
First Claim
1. A data processing apparatus comprising:
- a microprocessor for controlling the entire apparatus;
a first bus connected to said microprocessor;
at least one second bus which is not connected to said microprocessor;
a memory connected to both said first and second buses and allowing access from each of said buses;
at least one processing circuit connected to said second bus and adapted to perform a predetermined process with respect to given data under the control of said microprocessor; and
DMA means connected to said first and second buses and adapted to perform a data transfer process on said second bus to or from at least one of said processing circuit and said memory on the basis of an instruction through said first bus from said microprocessor.
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Accused Products
Abstract
Disclosed is a data processing apparatus which makes it possible to perform data processing at high speed by efficiently using a plurality of buses with a small number of microprocessors. The apparatus may be realized in the form of a facsimile apparatus including: a first bus connected to a microprocessor; a second bus which is not connected to the microprocessor; a memory connected to both the first and second buses; a memory control section which mediates between memory accesses from these buses so as to allow each of them to use the memory; a group of circuits for performing data processing through the second bus under the control of the microprocessor; and a DMA controller for effecting high-speed data transfer between each of the circuits and the memory.
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Citations
15 Claims
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1. A data processing apparatus comprising:
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a microprocessor for controlling the entire apparatus; a first bus connected to said microprocessor; at least one second bus which is not connected to said microprocessor; a memory connected to both said first and second buses and allowing access from each of said buses; at least one processing circuit connected to said second bus and adapted to perform a predetermined process with respect to given data under the control of said microprocessor; and DMA means connected to said first and second buses and adapted to perform a data transfer process on said second bus to or from at least one of said processing circuit and said memory on the basis of an instruction through said first bus from said microprocessor. - View Dependent Claims (2, 3)
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4. A data processing apparatus comprising:
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a first bus connected to a microprocessor for controlling the entire apparatus; at least one second bus which is not connected to said microprocessor; a memory connected to said first and second buses; and memory control means which mediate between memory access from said first bus and memory access from said second bus, wherein said memory control means and said memory perform operations corresponding to the accesses in accordance with a clock of a frequency higher than that of clocks supplied to predetermined circuits connected to said first and second buses so as to accept the accesses from said first bus and the accesses from said second bus in parallel.
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5. A facsimile apparatus for communicating image data comprising:
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a microprocessor for controlling the entire apparatus; a first bus connected to said microprocessor; at least one second bus which is not connected to said microprocessor; a memory connected to both said first and second buses and allowing access from each of the buses; reading means for reading original images; an image processing circuit for coding image data transmitted thereto through said second bus, under the control of said microprocessor; transmission means connected to said first bus and adapted to transmit information through a line; first DMA means for (a) DMA-transferring image data read by said image reading means to said memory through said second bus, (b) DMA-transferring the image data transferred to said memory to said image processing circuit through said second bus, and (c) DMA-transferring data coded by said image processing circuit to said memory through said second bus, under the control of said microprocessor; and second DMA means for DMA-transferring the coded data transferred to said memory by said first DMA means to said transmission means through said first bus, under the control of said microprocessor. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A facsimile apparatus for communicating image data comprising:
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a microprocessor for controlling the entire apparatus; a first bus connected to said microprocessor; at least one second bus which is not connected to said microprocessor; a memory connected to both said first and second buses and allowing access from each of these buses; receiving means connected to said first bus and adapted to receive coded image data through a line; an image processing circuit for decoding coded image data transmitted thereto from said second bus, under the control of said microprocessor; printing means for printing images; first DMA transfer means for DMA-transferring the coded image data received by said receiving means to said memory through said first bus, under the control of said microprocessor; and second DMA transfer means for (a) DMA-transferring coded image data stored by said first DMA means to said image processing circuit through said second bus, (b) DMA-transferring the image data decoded by said image processing circuit to said memory through said second bus, and (c) DMA-transferring the decoded image data transferred to said memory to said printing means through said second bus, under the control of said microprocessor. - View Dependent Claims (12, 13, 14, 15)
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Specification