Fuse and antifuse reprogrammable link for integrated circuits

• US 5,412,593 A
• Filed: 01/12/1994
• Issued: 05/02/1995
• Est. Priority Date: 01/12/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Magel, Gregory A., Stoltz, Richard A.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/180,581
• Time in Patent Office: 475 Days
• Field of Search: 365/96, 365/94, 365/102, 365/104, 365/225.7
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A fuse and antifuse link structure, which when used with a memory integrated circuit device such as a gate array or programmable mad-only memory (PROM), allows the memory circuit to be reprogrammed. The fuse and antifuse link is comprised of a fuse 12 and an antifuse 16, connected in series, parallel, or a combination thereof. Either element of the link can be programmed initially, and the other can be programmed in a second step, to reverse the first programming. Several links can be used in one circuit to provide multiple reprogramming capability.

Claims

1. A reprogrammable electrical circuit comprising:

a first terminal;

a second terminal;

a link, connected between said first terminal and said second terminal, wherein said link includes at least one fuse and at least one antifuse, said fuse and said antifuse being connected together in series, whereby the circuit is reprogrammable so as to alternatively open and close an electrically conductive path between said first terminal and said second terminal;

a first fuse and a first antifuse connected in series to form a first series sublink, said first series sublink connected on one end to said first terminal and on the other end to said second terminal;

a second fuse, connected in parallel with said first series sublink, wherein said link comprises said first sublink and said second fuse, whereby allowing reprogramming of said semiconductor device more than once; and

a second antifuse and a third fuse connected in series to form a second series sublink, said second series sublink connected in parallel with said first fuse, whereby allowing programming of said semiconductor device more than once.

2. A reprogrammable electrical circuit comprising:

a first terminal;

a second terminal;

a link, connected between said first terminal and said second terminal, wherein said link includes at least one fuse and at least one antifuse, said fuse and said antifuse being connected together in series, whereby the circuit is reprogrammable so as to alternatively open and close an electrically conductive .path between said first terminal and said second terminal;

a first antifuse and a first fuse connected in series between said first terminal and said second terminal;

a second fuse and a second antifuse connected in series to form a series sublink, said series sublink connected in parallel with said first fuse, wherein said link comprises said first antifuse, said first fuse and said series sublink, whereby allowing reprogramming of said semiconductor device more than once.

3. An array of sublinks for an integrated circuit, said array comprising:

a first terminal;

a second terminal;

at least two sublinks, wherein said sublinks consist of;

one fuse and one antifuse connected in series;

wherein said sublinks are connected in parallel and whereby the circuit is reprogrammable so as to selectively define an electrically conductive path between said input terminal and said output terminal.

4. The array of claim 3 wherein said integrated circuit is part of a gate array or PROM.

5. The array of claim 3 further comprising a programming terminal connected between said fuse and said antifuse.

6. A method of altering a connection within a semiconductor device in order to allow reprogrammability, comprising the steps of:

a) fabricating a semiconductor device with a first fuse and first antifuse connected in series to form a first series sublink, a second fuse and second antifuse connected in series to form a second series sublink, where said second antifuse is a higher voltage antifuse and blows at a higher voltage than said first antifuse;

where said first series sublink and said second series sublink are connected in parallel between said first terminal and said second terminal to allow reprogramming said semiconductor device more than once, and wherein said first series sublink connected between a first terminal and a second terminal;

b) applying a voltage across said first antifuse, blowing said first antifuse and programming said first antifuse closed;

then

c) applying a current through said first fuse, thereby blowing said first fuse and programming said first fuse open;

then

d) applying a voltage across said second antifuse, thereby blowing said second antifuse and programming said second antifuse closed;

then

e) applying a current through said second fuse, thereby blowing said second fuse and programming said second fuse open.

7. The method of claim 6 wherein said first series sublink is also comprised of a first programming terminal connected between said first fuse and said first antifuse, wherein said second series sublink is also comprised of a second programming terminal connected between said second fuse and said second antifuse, and wherein the connection of said device is altered by:

a) said applying a voltage across said first antifuse by utilizing said first programming terminal to apply a voltage to said first antifuse, thereby blowing said first antifuse and programming said first antifuse closed;

then

b) said applying a current through said first fuse thereby blowing said first fuse and programming said first fuse open;

then

c) utilizing said second programming terminal to apply a voltage to said second antifuse, thereby blowing said second antifuse and programming said second antifuse closed;

then

d) applying a current to said second fuse, thereby blowing said second fuse and programming said second fuse open.

8. The method of claim 7 wherein said applying a current through said first fuse is performed by applying the electrical signal across said first programming terminal and said second terminal.

9. The method of claim 7 wherein said applying a current through said first fuse is performed by applying the electrical signal across said first terminal and said second terminal.

10. The method of claim 7 wherein said applying a current to said second fuse is performed by applying the electrical signal across said second programming terminal and said second terminal.

11. The method of claim 7 wherein said applying a current to said second fuse is performed by applying the electrical signal across said first terminal and said second terminal.

12. A method of altering a connection within a semiconductor device in order to allow reprogrammability, comprising the steps of:

a) fabricating a semiconductor device with a first fuse and first antifuse connected in parallel to form a first parallel sublink, a second fuse and a second antifuse connected in parallel to form a second parallel sublink, where said second fuse is a higher current fuse and blows at a higher current than said first fuse, where said first parallel sublink and said second parallel sublinks are connected in series between said first terminal and said second terminal to allow reprogramming said semiconductor device more than once;

b) applying a current through said first fuse, thereby blowing said first fuse and programming said first fuse open, then;

c) applying a voltage across said first antifuse, blowing said first antifuse and programming said first antifuse closed, then;

d) applying a current through said second fuse, thereby blowing said second fuse and programming said second fuse open;

then

e) applying a voltage across said second antifuse, thereby blowing said second antifuse and programming said second antifuse closed.

13. The method of claim 12 further comprising a first programming terminal connected between said first parallel sublink and said second parallel sublink, and wherein the connection of said device is altered by:

b) said applying a current through said first fuse by applying a current through said first terminal and said first programming terminal to said first fuse, thereby blowing said first fuse and programming said first fuse open;

then

c) said applying a voltage across said first antifuse, thereby blowing said first antifuse and programming said first antifuse closed;

then

d) applying a current to said second fuse through said first programming terminal and said second terminal, thereby blowing said second fuse and programming said second fuse open;

then

e) applying a voltage across said second antifuse, thereby blowing said second antifuse and programming said second antifuse closed.

14. The method of claim 13 wherein said applying a voltage across said first antifuse is performed by applying said voltage across said first terminal and said first programming terminal.

15. The method of claim 13 wherein said applying a voltage across said first antifuse is performed by applying said voltage across said first terminal and said second terminal.

16. The method of claim 13 wherein said applying a voltage across said second antifuse is performed by applying said voltage across said first programming terminal and said second terminal.

17. The method of claim 13 wherein said applying a voltage across said second antifuse is performed by applying said voltage across said first terminal and said second terminal.

18. A method of altering a connection within a semiconductor device in order to allow reprogrammability, comprising the steps of;

a) fabricating a semiconductor device with a first fuse and first antifuse connected in series to form a first series Sublink, wherein said first series sublink is connected in parallel with a second fuse between a first terminal and a second terminal, further comprising a second antifuse and a third fuse connected in series to form a second series sublink, said second series sublink;

b) applying a current through said second fuse by applying an electrical signal across said first terminal and said second terminal, thereby blowing said second fuse and programming said second fuse open;

then

c) applying a voltage across said first antifuse by applying said voltage across said first terminal and said second terminal, thereby blowing said first antifuse and programming said first antifuse closed;

then

d) applying a current through said first fuse by applying an electrical signal across said first terminal and said second terminal, thereby blowing said first fuse and programming said first fuse open;

then

e) applying a voltage to said second antifuse by applying said voltage across said first terminal and said second terminal, thereby blowing said second antifuse and programming said second antifuse closed;

then,

f) applying a current to said third fuse by applying an electrical signal across said first terminal and said second terminal, thereby blowing said third fuse and programming said third fuse open.

19. A method of altering a connection within a semiconductor device in order to allow reprogrammability, comprising the steps of:

a) fabricating a semiconductor device with a first fuse and first antifuse connected in series between a first terminal and a second terminal, a second fuse and second antifuse connected in series to form a series sublink, where said series sublink connected in parallel with said first fuse;

applying a voltage across said first antifuse by applying said voltage across said first terminal and said second terminal, thereby blowing said first antifuse and programming said first antifuse closed;

then

c) applying a current through said first fuse by applying an electrical signal across said first terminal and said second terminal, thereby blowing said first fuse and programming said first fuse open;

then

d) applying a voltage across said first terminal and said second terminal, thereby blowing said second antifuse and programming said second antifuse closed;

then

e) applying a current through said first terminal and said second terminal, thereby blowing said second fuse and programming said second fuse open.

20. A reprogrammable electrical circuit comprising:

a first terminal;

a second terminal;

a link, connected between said first terminal and said second terminal, wherein said link includes at least one fuse and at least one antifuse, said fuse and said antifuse being connected together in parallel, whereby the circuit is reprogrammable so as to alternatively open and close an electrically conductive path between said first terminal and said second terminal

a first fuse and a first antifuse connected in series to form a first series sublink, said first series sublink connected on one end to said first terminal and on the other end to said second terminal;

a second fuse, connected in parallel with said first series sublink, wherein said link comprises said first sublink and said second fuse, whereby allowing reprogramming of said semiconductor device more than once; and

a second antifuse and a third fuse connected in series to form a second series sublink, said series sublink connected in parallel with said first fuse, whereby allowing programming of said semiconductor device more than once.

21. A reprogrammable electrical circuit comprising:

a first terminal;

a second terminal;

a link, connected between said first terminal and said second terminal, wherein said link includes at least one fuse and at least one antifuse, said fuse and said antifuse being connected together in parallel, whereby the circuit is reprogrammable so as to alteratively open and close an electrically conductive path between said first terminal and said second terminal;

a first antifuse and a first fuse connected in series between said first terminal and said second terminal; and

a second fuse and a second antifuse connected in series to form a series sublink, said series sublink connected in parallel with said first fuse, wherein said link comprises said first antifuse, said first fuse and said series sublink, whereby allowing reprogramming of said semiconductor device more than once.

22. An array of sublinks for an integrated circuit, said array comprising:

a first terminal;

a second terminal;

at least two sublinks, wherein said sublinks consist of one fuse and one antifuse connected in parallel;

wherein said sublinks are connected in series and whereby the circuit is reprogrammable so as to selectively define an electrically conductive path between said input terminal and said output terminal.

23. The array of claim 22 further comprising a programming terminal between said sublinks.