Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias

• US 5,414,221 A
• Filed: 07/15/1993
• Issued: 05/09/1995
• Est. Priority Date: 12/31/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Figlin, Cheryl R.
• Application Number:
  US08/093,266
• Time in Patent Office: 663 Days
• Field of Search: 174/261, 174/262, 174/264, 174/35 R, 174/265, 257/668, 257/684, 257/700, 257/703
• US Class Current: 174/261
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, electrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures. A variety of deposition methods are set forth including methods employing an anisotropic etch and methods employing an etch-stop/masking layer. Resulting structures are also described.

Claims

1. A multi-layer structure comprising:

a substrate having a top surface having first and second portions;

a first dielectric layer, an electrically conducting layer, and a second dielectric layer, formed in parallel on said first portion of said substrate leaving an aperture having substantially vertical sidewalls around said second portion of said substrate; and

an insulating layer extending along said substantially vertical sidewalls of said aperture from said substrate to a top surface of said second dielectric.

2. The multi-layer structure of claim 1 further comprising:

a conducting material filling said aperture and extending from said second portion of said substrate to said top surface of said second dielectric.

3. A multi-layer structure comprising:

a substrate having a top surface having first and second portions;

a first dielectric and a conducting layer formed in parallel on said second portion of said substrate;

a second dielectric formed on a top portion of said conducting layer and having substantially vertical sidewalls adjacent to said first portion of said top surface of said substrate; and

a second dielectric formed on a top portion of said conducting layer, said second dielectric extending along vertical side edges of said first dielectric and said electrically conducting layer to said first portion of said substrate and extending along a portion of said second portion of said substrate, with said second dielectric having a substantially L-shaped cross section taken perpendicular to said top surface of said substrate.

4. The multi-layer structure of claim 3 further comprising:

a conducting material formed on said second portion of said top surface of said substrate, said conducting material extending between a pair of opposing L-shaped portions of said second dielectric.

5. The multi-layer structure of claim 4 further comprising a conducting layer formed on a top surface of said second dielectric and on a top surface of said conducting material.

6. The multi-layer structure of claim 5 further comprising a metal interconnect connecting a portion of said upper conducting layer to said conducting layer.

7. A multi-layer structure comprising:

a substrate having a top surface with first and second portions;

a first dielectric and a conducting layer formed in parallel on said second portion of said substrate and having substantially vertical side edges adjacent to said first portion of said substrate;

a second dielectric layer having a first portion extending along a first portion of a top surface of said conducting layer, said first portion of said second dielectric extending along said substantially vertical side edges of said conducting layer and said first dielectric, and extending along a portion of said second portion of said substrate;

wherein said second dielectric has a second portion extending along a second portion of a top surface of said conducting layer to a position offset from a side edge of said conducting layer thereby exposing a portion of said conducting layer; and

a conducting material formed on said second portion of said substrate between said vertical portion of said first portion of said second dielectric and a side edge of said second portion of said second dielectric, said conducting material contacting said second portion of said conducting material.

8. A multi-layer structure comprising:

a substrate having a top surface with first and second portions;

a first dielectric layer and a conducting layer formed in parallel on said first portion of said top surface of said substrate; and

a second dielectric layer formed along a top surface of said conducting layer, said second dielectric extending along said vertical sidewalls of said first dielectric and said conducting layer to said second portion of said top surface of said substrate, said second dielectric layer having portions formed on said second portion of said top surface of said substrate but offset from said sidewalls of said first dielectric layer and said conducting layer.

9. A multi-layer structure comprising:

a substrate;

a ground plane coveting a substantially L-shaped portion of a top surface of said substrate; and

an interconnect covering a substantially L-shaped portion of a top surface of said ground plane, said interconnect being offset from opposing side edges of said ground plane.