TFT with reduced parasitic capacitance

• US 5,414,283 A
• Filed: 11/19/1993
• Issued: 05/09/1995
• Est. Priority Date: 11/19/1993
• Status: Expired due to Term

• Current Assignee: First Chicago/NBD Bank N.A., InnoLux Corporation
• Original Assignee: OIS Optical Imaging Systems, Inc. (KOCH Industries Incorporated)
• Inventors: den Boer, Willem, Yang, Mohshi
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US08/154,713
• Time in Patent Office: 536 Days
• Field of Search: 257/57, 257/59, 257/66, 257/72, 257/347, 257/401, 359/59
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode substantially completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.

Claims

1. A pixel for use in a liquid crystal display, comprising:

a layer of liquid crystal material sandwiched between two spaced substrates, one of said substrates having a pixel electrode mounted thereon which defines a pixel surrounded by, ate and drain lines, wherein said pixel electrode is electrically connected to a thin film transistor, said thin film transistor comprising;

a drain electrode adapted to be electrically connected to said drain line;

a gate electrode adapted to be electrically connected to said gate line; and

a source electrode electrically connected to said pixel electrode;

wherein said source electrode is located on a semiconductor film and is substantially completely surrounded in substantially all lateral directions by said drain electrode, and wherein said drain electrode is disposed between said source electrode and at least a substantial portion of said pixel electrode so that said transistor has a reduced parasitic capacitance.

2. The pixel of claim 1 wherein said drain electrode is substantially annular or circular defining an inner and outer diameter, and said source electrode is substantially round defining an outer diameter.

3. The pixel of claim 1 wherein said thin film transistor further comprises a passivation insulating layer formed on an upper surface of at least one of said drain and source electrodes, and said pixel electrode electrically connected to said source electrode is transparent and is adhered to and crosses over said passivation layer and said drain electrode.

4. The pixel of claim 3, wherein said transparent pixel electrode consists essentially of Indium-Tin-Oxide (ITO) and said passivation layer consists essentially of one of:

silicon nitride, silicon oxide, and combinations thereof.

5. The pixel of claim 3, wherein said thin film transistor has a parasitic capacitance C_GS (max) less than about 65 fF, and an ON current I_ON (-) greater than about 7.0 μ

A when V_G =20 volts, V_S =0, and V_D =10 volts.

6. The pixel of claim 5 wherein said thin film transistor has a parasitic capacitance C_GS (max) less than or equal to about 60 fF, and an ON current I_ON (-) greater than about 10.5 μ

A.

7. The pixel of claim 3, wherein said thin film transistor further comprises a gate insulating layer disposed between said semiconductor film and said gate electrode, wherein said gate insulating layer includes a silicon nitride layer and a TaO layer.

8. The pixel of claim 7, wherein said TaO layer is about 1,600 Å

thick and said silicon nitride layer is about 2,000 Å

thick.

20. The pixel of claim 1, wherein the gate electrode, not including the gate line, has a larger horizontal surface area than the semiconductor layer.

21. The pixel of claim 20, wherein said semiconductor layer does not extend laterally on any side to the periphery of said gate electrode, and is thereby shielded by said gate electrode from radiation emitted from a backlighting means.

9. In an active matrix liquid crystal display (AMLCD) comprising a plurality of thin film transistors arranged on an insulating substrate in the form of a matrix, at least one of said plurality of thin film transistors including a drain electrode electrically connected to a drain line, a gate electrode electrically connected to a gate line, and a source electrode electrically connected to a transparent pixel electrode of a corresponding picture element or pixel, wherein said source and drain electrodes of said at least one thin film transistor are formed on a semiconductor film and separated from one another by a channel defining a predetermined length and width, the improvement comprising:

wherein said source electrode of said at least one thin film transistor is centrally located on said semiconductor film and is substantially completely surrounded laterally by said drain electrode, and wherein said drain electrode is positioned between said source electrode and said picture element.

10. The display of claim 9 wherein said drain electrode is substantially annular or circular defining an inner and an outer diameter, and said source electrode is substantially round defining only an outer diameter.

11. The display of claim 9 wherein said gate line is arranged in a row direction, said drain line is arranged in a column direction substantially perpendicular to said gate line, and wherein said gate and drain lines intersect one another defining said pixel display area therebetween.

12. The display of claim 11 wherein said thin film transistor is located at the intersection of said gate and drain lines thereby enlarging the size of said pixel display area and wherein the picture element is disposed in the rectangular area defined between said gate and drain lines.

13. The display of claim 9 further comprising a passivation layer formed on an upper surface of at least one of said drain and source electrodes, and wherein a portion of said transparent pixel electrode crosses over said drain electrode and said passivation layer.

14. The display of claim 13 wherein said pixel electrode consists essentially of Indium-Tin-Oxide (ITO) and said passivation layer consists essentially of one of:

silicon nitride, silicon oxide, and combinations thereof.

15. The display of claim 9 wherein said channel is ring-shaped, and said source is round having a diameter of about 5-12 μ

m.

16. The display of claim 9 wherein said semiconductor film consists essentially of amorphous silicon and is about 2,000 Å

thick.

17. The display of claim 10 wherein said gate electrode is substantially round and has a diameter substantially larger than said inner diameter of said drain electrode thereby increasing the tolerance for misalignment of said source and drain electrodes relative to said gate electrode.

18. The display of claim 9 wherein said thin film transistor has a parasitic capacitance C_GS (max) less than about 65 fF, and an ON current, I_ON (-), greater than about 7.0 μ

A when V_G =20 volts, V_S =0 volts, and V_D =10 volts.

19. The display of claim 18 wherein said thin film transistor has a parasitic capacitance C_GS (max) less than or equal to about 60 fF and an ON current I_ON (-) greater than about 11.0 μ

A.

22. A liquid crystal display comprising:

a plurality of TFTs which act as switching elements for corresponding pixels, said TFTs being laterally spaced from the picture defining portions of said pixels; and

wherein each of said TFTs includes a gate electrode and a centrally located source electrode substantially surrounded by a drain electrode whereby said TFTs have reduced parasitic capacitances.