Process for high density split-gate memory cell for flash or EPROM

• US 5,414,287 A
• Filed: 04/25/1994
• Issued: 05/09/1995
• Est. Priority Date: 04/25/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/231,812
• Time in Patent Office: 379 Days
• Field of Search: 257/316, 257/322, 257/324, 257/328, 257/330, 257/331, 437/43, 437/42, 437/228
• US Class Current: 257/316
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method and structure for manufacturing a high-density split gate memory cell, for a flash memory or EPROM, is described. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over a portion of the vertical surfaces of the first dielectric layer, and acts as a floating gate for the high density split-gate memory cell. A source region is located in the silicon substrate, and is implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is located in the top of the silicon islands, and is also implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A second dielectric layer is formed over the top and side surfaces of the floating gate, and acts as an interpoly dielectric. A second conductive layer is formed over that remaining portion of the vertical surfaces of the first dielectric layer not covered by the first conductive layer, and surrounds the second dielectric layer, whereby the second conductive layer is a control gate.

Claims

1. A high density split-gate memory cell, for an erasable programmable read-only memory (EPROM) or flash-memory, comprising:

a silicon island formed from a silicon substrate

implanted with a first conductivity-imparting dopant;

a first dielectric layer surrounding vertical surfaces of said silicon islands, whereby said first dielectric layer is a gate oxide;

a first conductive layer formed over a portion of the vertical surfaces of said first dielectric layer, acting as a floating gate for said high density split-gate memory cell;

a source region in said silicon substrate, implanted with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant, surrounding the base of said silicon island;

a drain region in the top of said silicon island, implanted with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant;

a channel region between said source and drain regions, under the vertical surfaces of said silicon island, whereby said floating gate is coupled to only a first lower portion of said channel region;

a second dielectric layer over the top and side surfaces of said floating gate, acting as an interpoly dielectric; and

a second conductive layer formed over that remaining portion of said vertical surfaces of said first dielectric layer not covered by said first conductive layer, and surrounding said second dielectric layer, coupled to that portion of said channel region not coupled to said floating gate, whereby said second conductive layer is a control gate.

2. The high density split-gate memory cell of claim 1, wherein said silicon island has a height of between about 0.5 and 2.0 micrometers.

3. The high density split-gate memory cell of claim 1, wherein said gate oxide has a thickness of between about 50 and 120 Angstroms.

4. The high density split-gate memory cell of claim 1, wherein said first conductive layer is doped polycrystalline silicon having a thickness of between about 500 and 2000 Angstroms.

5. The high density split-gate memory cell of claim 1, wherein said source and drain regions are ion implanted with arsenic at a concentration of between about 1×

10¹⁵ and 8×

10¹⁵ atoms/cm.² and an energy of between about 30 and 100 KeV.

6. The high density split-gate memory cell of claim 1, wherein said interpoly dielectric comprises:

a first layer of silicon oxide, adjacent to said first conductive layer;

a layer of silicon nitride, over said first layer of silicon oxide; and

a second layer of silicon oxide, over said layer of silicon nitride.

7. The high density split-gate memory cell of claim 1, wherein said second conductive layer is formed of doped polycrystalline silicon, and has a thickness of between about 2000 and 4000 Angstroms.

8. A method of forming a high density split-gate memory cell, for an electrically programmable read-only memory (EPROM) or flash-memory, comprising the steps of:

forming silicon islands from a silicon substrate implanted with a first conductivity-imparting dopant;

forming source regions in said silicon substrate in the regions between said silicon islands, by implanting with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant, and simultaneously forming drain regions in the top of said silicon islands by said implanting with a second and opposite conductivity-imparting dopant;

forming a first dielectric layer surrounding vertical surfaces of said silicon islands;

forming a first conductive layer over a portion of the vertical surfaces of said first dielectric layer, thereby creating a floating gate for said high density split-gate memory cell;

forming a second dielectric layer over the top and side surfaces of said floating gate; and

forming a second conductive layer over that remaining portion of said vertical surfaces of said first dielectric layer not covered by said first conductive layer, and surrounding said second dielectric layer, whereby said second conductive layer is a control gate.

9. The method of claim 8 wherein said forming a first conductive layer comprises the steps of:

depositing a layer of polycrystalline silicon over said first dielectric layer to a thickness of between about 500 and 2000 Angstroms;

doping said layer of polycrystalline silicon by doping with phosphorus oxychloride (POC13) at between about 800 and 950°

C. for between about 10 and 20 minutes, to reduce the sheet resistance to between about 30 and 1000 ohms/square;

etching said layer of polycrystalline silicon by anisotropically etching at a pressure of about 400 mtorr, a power of about 300 watts, using Helium (He) at about 400 cc./min., chlorine (C12) at about 200 cc./min., and hydrogen bromide (HBr) at about 100 cc./min., with end point detector as an etch completeness reference; and

overetching said layer of polycrystalline silicon for between about 50 and 300 seconds, such that said layer of polycrystalline silicon covers said portion of the vertical surfaces of said first dielectric layer.

10. The method of claim 8 wherein said first dielectric layer is formed to a thickness of between about 50 and 120 Angstroms, by thermal oxidation, at a temperature of between about 800°

and 900°

C., in dry oxygen.

11. The method of claim 8, wherein said silicon island is formed to a height of between about 0.5 and 2.0 micrometers.

12. The method of claim 8, wherein said source and drain regions are ion implanted with arsenic at a concentration of between about 1×

10¹⁵ and 8×

10¹⁵ atoms/cm.² and an energy of between about 30 and 100 KeV.

13. The method of claim 8, wherein said forming a second dielectric layer comprises the steps of:

forming a first layer of silicon oxide, adjacent to said first conductive layer and over the exposed surfaces of said first dielectric layer, to a thickness of between about 50 and 150 Angstroms;

forming a layer of silicon nitride, over said first layer of silicon oxide, to a thickness of between about 60 and 200 Angstroms;

forming a second layer of silicon oxide, over said layer of silicon nitride, to a thickness of between about 30 and 100 Angstroms; and

14. The method of claim 8, wherein said second conductive layer is formed of doped polycrystalline silicon, and is formed to a thickness of between about 2000 and 4000 Angstroms.

15. An electrically programmable read-only memory (EPROM) or flash-memory, with an array of high density split-gate memory cells, comprising:

silicon islands formed from a silicon substrate having been implanted with a first conductivity-imparting dopant;

a first dielectric layer surrounding vertical surfaces of said silicon islands, whereby said first dielectric layer is a gate oxide;

a first conductive layer formed over a portion of the vertical surfaces of said first dielectric layer, acting as floating gates for said high density split-gate memory cells;

source regions in said silicon substrate, implanted with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant, surrounding the base of said silicon islands;

drain regions in the top of said silicon islands, implanted with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant;

channel regions between said source and drain regions, under the vertical surfaces of said silicon islands, whereby said floating gate is coupled to only a first lower portion of said channel region;

a second dielectric layer over the top and side surfaces of said floating gates, acting as an interpoly dielectric; and

a second conductive layer formed over that remaining portion of said vertical surfaces of said first dielectric layer not covered by said first conductive layer, and surrounding said second dielectric layer, coupled to that portion of said channel region not coupled to said floating gate, whereby said second conductive layer acts as a control gate and word line for said high density split-gate memory cells, and connects together a column of said memory cells;

a thermal oxide layer over said second conductive layer;

an insulating layer of borophosphosilicate glass over said memory cells and and said word lines;

16. The device of claim 15 wherein said providing means are used to program said memory cells by applying a voltage of between about 12 and 15 volts to said word line, a voltage of 6 volts to said drain region, and 0 volts to said source region.

17. The device of claim 15 wherein said providing means are used to erase said memory cells by applying a voltage of 0 volts to said word line, a floating voltage to said drain region, and a voltage of 12 volts to said source region.

18. The device of claim 15 wherein said providing means are used to read said memory cells by applying a voltage of 3 volts to said word line, a voltage of 1 volt to said drain region, and 0 volts to said source.

19. The device of claim 18 further comprising a means to detect current flow through said memory cells during said read operation.

20. The device of claim 19 wherein said detecting means are used to determine if said memory cell is off or on.

21. A high density split-gate memory cell, for an erasable programmable read-only memory (EPROM) or flash-memory, formed by the method comprising the steps of:

forming silicon islands from a silicon substrate implanted with a first conductivity-imparting dopant;

forming source regions in said silicon substrate in the regions between said silicon islands, by implanting with a second and opposite conductivity-imparting dopant to said first conductivity-imparting dopant, and simultaneously forming drain regions in the top of said silicon islands by said implanting with a second and opposite conductivity-imparting dopant;

forming a first dielectric layer surrounding vertical surfaces of said silicon islands;

forming a first conductive layer over a portion of the vertical surfaces of said first dielectric layer, thereby creating a floating gate for said high density split-gate memory cell;

forming a second dielectric layer over the top and side surfaces of said floating gate; and

forming a second conductive layer over that remaining portion of said vertical surfaces of said first dielectric layer not covered by said first conductive layer, and surrounding said second dielectric layer, whereby said second conductive layer is a control gate.