IGBT with self-aligning cathode pattern and method for producing it

• US 5,414,290 A
• Filed: 04/07/1994
• Issued: 05/09/1995
• Est. Priority Date: 05/07/1993
• Status: Expired due to Term

• Current Assignee: ABB Schweiz AG (ABB Limited)
• Original Assignee: ABB Management AG (ABB Limited)
• Inventors: Bauer, Friedhelm
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/224,300
• Time in Patent Office: 397 Days
• Field of Search: 257/341, 257/398, 257/401, 437/40, 437/233, 437/913
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

An insulated-gate bipolar transistor (IGBT) is specified, the collector (7) and source regions (8) of which can be produced by means of a self-aligning method. This provides an IGBT which is distinguished by a homogeneous turn-off current distribution. For this purpose, the width W of the source regions (8) is selected to be so small that holes can flow laterally into the surrounding collector region. In this connection it must be ensured that the voltage drop across the PN junction of the source regions and collector regions remains below the inherent forward voltage at any time. In consequence, the IGBT according to the invention is particularly insensitive to latch-up.

Claims

1. An insulated-gate bipolar transistor comprising

a semiconductor substrate of a first conduction type which is bounded by a first and a second main area;

a cathode which is allocated to the first main area, and an anode which is formed by a metallization covering the second main area;

an emitter layer of a second conduction type which is inserted into the semiconductor substrate from the anode-side main area;

a plurality of collector regions of the second conduction type which are inserted into the semiconductor substrate from the cathode-side main area, the semiconductor substrate penetrating to the cathode-side main area between two adjacent collector regions;

a gate electrode which is formed by a conducting layer which is arranged and insulated above the cathode-side main area and extends from a collector region over the semiconductor substrate penetrating to the surface to the adjacent collector region;

a number of source regions of the first conduction type which are inserted into the collector regions and which exhibit a length L and at right angles thereto a width W in the direction of an adjacent collector region;

wherein

the length L of the source regions is selected such that there are at least two channel regions produced for each source region, the channel regions comprising a part of a collector region which penetrates to the cathode-side main area between the source region and semiconductor substrate and which is covered by the gate electrode,

the width of the source regions is selected to be of the order of magnitude of microns such that holes which flow from the anode to the cathode underneath the source regions polarize a PN-junction which is formed by the source regions and the adjacent collector regions in the forward direction, and such that a voltage drop across said PN-junction remains below the inbuilt forward voltage of the PN junction at any time.

2. IGBT as claimed in claim 1, wherein

the collector regions are designed to be strip-shaped.

3. IGBT as claimed in claim 2, wherein the source regions of two adjacent collector regions are in each case arranged alternately opposite.

4. IGBT as claimed in claim 2, wherein the source regions of two adjacent collector regions are in each case arranged to be directly opposite.

5. IGBT as claimed in claim 1, wherein

the collector regions form a closed area, this area exhibiting a number of holes in which the semiconductor substrate penetrates to the cathode-side surface;

these holes are covered with the conducting gate electrode layer and form gate electrode islands; and

two adjacent gate electrode islands are connected via narrow bridges of the conducting layer.

6. IGBT as claimed in claim 5, wherein the bridges are so narrow that the collector regions flow together underneath the bridges in a diffusion step during the production.

7. IGBT as claimed in claim 5, wherein the gate electrode islands exhibit the form of a circle or of a polygon, especially of a hexagon.

8. IGBT as claimed in claim 5 wherein the source regions are designed as narrow strips which essentially extend from one gate electrode island to the diagonally opposite one.

9. IGBT as claimed in claim 6 wherein the source regions are designed as narrow strips which essentially extend from one gate electrode island to the diagonally opposite one.

10. IGBT as claimed in claim 7 wherein the source regions are designed as narrow strips which essentially extend from one gate electrode island to the diagonally opposite one.

11. IGBT as claimed in claim 5, wherein the source regions are designed as narrow crosses which extend from one gate electrode island to the diagonally opposite one.

12. IGBT as claimed in claim 6, wherein the source regions are designed as narrow crosses which extend from one gate electrode island to the diagonally opposite one.

13. IGBT as claimed in claim 7, wherein the source regions are designed as narrow crosses which extend from one gate electrode island to the diagonally opposite one.

14. Method for producing an IGBT which comprises the steps of:

patterning a cathode-side surface after creation of the anode and any edge termination, by means of the following steps;

deposition of a gate oxide layer;

deposition of a polysilicon layer which is covered with an SiO₂ masking layer;

removal of the polysilicon layer at the locations where no gate electrode is to be created;

implantation and diffusion of the collector regions, the polysilicon layer being used as implantation mask;

covering of the collector regions with resist at the locations where no source region is to be created;

implantation and diffusion of the source regions and simultaneous doping of the silicon layer to become the gate electrode, the polysilicon layer for the source regions, in turn, being used as implantation masks; and

insulation of the gate electrode, contact hole opening and metallization of the cathode.

15. A method as claimed in claim 14, further comprising subjecting the collector regions to an additional implantation step after the implantation and diffusion of the source regions.