High frequency clock generator with multiplexer

• US 5,414,308 A
• Filed: 07/29/1992
• Issued: 05/09/1995
• Est. Priority Date: 07/29/1992
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Shen, Tim H. T., Huang, Stephen R. M., Lee, I-Shi, Kuo, Judy C. L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/921,889
• Time in Patent Office: 1,014 Days
• Field of Search: 328/61, 328/62, 328/63, 328/72, 328/137, 328/104, 328/154, 307/269, 307/241, 307/243, 307/271, 331/162, 331/49, 331/46, 331/54, 331/56
• US Class Current: 327/293
• CPC Class Codes: H03B 1/04 Reducing undesired oscillations, e.g. harmonics
• CPC Class Codes: H03B 2201/0283 the means functioning digitally
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00

Abstract

A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.

Claims

1. A high frequency clock generator comprising:

a plurality of clock oscillator circuits, each of said clock oscillator circuits including an output terminal for transmitting an output clock signal from the clock oscillator circuit;

a first multiplexer comprising a plurality of input terminals coupled on a one-to-one basis to the plurality of output terminals of said plurality of clock oscillator circuits, said first multiplexer also comprising an output terminal providing an output clock signal at a first predetermined oscillation frequency; and

a second multiplexer comprising a plurality of input terminals coupled on a one-to-one basis to the output terminals of said plurality of clock oscillator circuits, said second multiplexer also comprising an output terminal providing a second predetermined oscillation frequency,

wherein said plurality of clock oscillator circuits and said first multiplexer and said second multiplexer are formed as an integrated circuit.

2. Structure of claim 1 wherein said plurality of input terminals of said first multiplexer comprises a plurality of input pads.

3. Structure of claim 1 wherein said first multiplexer further comprises means to select one of said plurality of clock oscillator circuits.

4. Structure of claim 1 wherein said first multiplexer is a multiple-to-one multiplexer.

5. Structure of claim 1 wherein said plurality of input terminals of said second multiplexer comprises a plurality of input pads.

6. Structure of claim 1 wherein said second multiplexer further comprises means to select one of said plurality of clock oscillator circuits.

7. Structure of claim 1 wherein said second multiplexer is a multiple-to-one multiplexer.

8. A high frequency clock generator including a plurality of oscillators, said clock generator comprising:

a plurality of clock oscillator circuits, each clock oscillator circuit having a pair of input lines and an output line, said pair of input lines coupled to one of said plurality of oscillators; and

a plurality of multiplexers, each multiplexer comprising a plurality of input terminals, each of said input terminals of one of said multiplexers being coupled on a one-to-one basis to said output lines;

wherein said plurality of clock oscillator circuits and said plurality of multiplexers are formed as an integrated circuit.

9. Structure of claim 8 wherein said oscillator is a quartz crystal.

10. Structure of claim 8 where each of said plurality of multiplexers comprises a plurality of select pins and an output line.

11. Structure of claim 9 wherein the number of said plurality of oscillators is equal to the number of said multiplexers.

12. Structure of claim 9 wherein the number of said plurality of oscillators is greater than the number of said multiplexers.

13. A method of generating a clock signal comprising:

forming a plurality of crystal oscillator circuits as an integrated circuit, said crystal oscillator circuits generating a plurality of signals of predetermined frequencies, each of said crystal oscillator circuits comprising a pair of input lines;

connecting a plurality of quartz crystals on a one-to-one basis to said pair of input lines of each of said crystal oscillator circuits;

a first multiplexing step for multiplexing said plurality of signals to provide a first output signal; and

a second multiplexing step simultaneously with said first multiplexing step for multiplexing said plurality of signals at the same time as said first output signal to provide a second output signal.

14. Method of claim 13 wherein said first multiplexing step comprises coupling one multiplexer to said plurality of crystal oscillators.

15. Method of claim 14 wherein each of said plurality of signals of said plurality of crystal oscillators generates a corresponding output signal having a predetermined frequency.