Weighting system for testing of circuits utilizing determination of undetected faults

• US 5,414,716 A
• Filed: 09/22/1993
• Issued: 05/09/1995
• Est. Priority Date: 09/22/1993
• Status: Expired due to Term

• Current Assignee: Mitsubishi Electric Research Laboratories, Inc. (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Electric Research Laboratories (Mitsubishi Electric Corporation)
• Inventors: Bershteyn, Mikhail
• Primary Examiner(s): Ramirez, Ellis B.
• Assistant Examiner(s): Assouad, Patrick J.
• Application Number:
  US08/107,240
• Time in Patent Office: 594 Days
• Field of Search: 364/717, 364/718, 371/27, 371/23, 371/25.1
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern

Abstract

In integrated circuit testing, a system is provided for reducing testing time by decreasing the number of test vectors or patterns while maintaining high fault coverage through utilizing lists of undetected faults in an integrated circuit to determine the optimal weighting for a weighted random pattern generator that is used for testing the integrated circuit. Undetected faults are derived from testing a model of the circuit under test with a uniform weight pattern, with the circuit modified with each fault from a list of anticipated faults. Undetected faults from this first pass are used to generate another set of weights which are then used to apply test signals to the circuit for generating a further but diminished list of undetected faults. This process is iterative and is continued until the number of undetected faults is either zero or some low acceptable number. The set of weights generated in this iterative process is then used in the weighted random pattern generator for applying test signals to actual circuits. As part of this process, for circuit elements requiring diametrically opposed input signals, such as AND gates and OR gates where a single set of input signals is inappropriate, this conflict is resolved through detecting the fact that for one part, all faults are detected, and then generating test vectors suitable for the opposite circuit. This allows the testing of circuits piece by piece.

Claims

1. A system for reducing testing time of digital integrated circuits by decreasing the number of test vectors utilized while maintaining high fault coverage without deterministic testing, comprising:

means for first determining all faults for a predetermined integrated circuit and for generating a set of calculated weights;

means for testing said integrated circuit with said set of calculated weights for generating a reduced list of undetected faults;

means for iteratively testing said integrated circuit with calculated weights from successively reduced lists of undetected faults by calculating additional weights directly from the reduced list of undetected faults from the previous iteration, said iteration to continue until a predetermined low number of undetected faults exists;

a weighted pattern generator for producing test vectors coupled to inputs to said integrated circuit; and

,

means for applying said calculated sets of weights to said weighted pattern generator, thereby to provide said generator with an optimal set of weights that decrease the number of test vectors provided by said weighted pattern generator to reduce said testing time.

2. The system of claim 1, wherein said integrated circuit includes two sets of circuits having opposite responses to the same set of input signals and further including means for determining optimal weighting test vectors for each of said two sets of circuits, and means for isolating said two sets of circuits during testing based on said determination.

3. The system of claim 2, wherein said integrated circuit has an input block having a fanout stem, a series of branches associated therewith, and a series of blocks, each associated with a different branch and each including different subcircuits, said system further including:

means for separately examining weights calculated for each of said branches of said integrated circuit to ascertain and indicate if a set of weights for any branch indicates a weight bias towards more frequent generation of logic level "1" signals, while weights for other branches indicate more frequent generation of logic level "0" signals; and

means for dropping from testing all branches having sets of weights with a weight bias toward more frequent generation of a "1" or "0".

4. The system of claim 3, wherein said dropping means operates on the basis of selecting for testing those branches having circuits with a larger number of detectable faults.

5. The system of claim 4, wherein the branches having the larger number of detectable faults are associated with an identifiable fanout stem, wherein said identifiable fanout stem is provided with a selected set of weights and further including means after having a selected set of weights for said identifiable fanout stem for adjusting the weights for associated branches such that the sets of weights for associated branches are consistent with the set of weights for said fanout stem.