Asynchronous samples data demodulation system

• US 5,414,730 A
• Filed: 12/21/1993
• Issued: 05/09/1995
• Est. Priority Date: 12/21/1993
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Kingston, Samuel C., Lundquist, Alan E., Zscheile, John W. Jr.
• Primary Examiner(s): Swann, Tod R.
• Application Number:
  US08/170,604
• Time in Patent Office: 504 Days
• Field of Search: 375/1, 380/34
• US Class Current: 375/150
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/70752 Partial correlation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure

Abstract

A novel PN code acquisition and demodulation circuit comprise an analog receiver coupled to an analog to digital converter. The digital output of the converter is passed through an N chip width parallel correlator. The parallel outputs are coherently accumulated to provide N soft decision data values one of which is indicative of the proper replica code for locking onto the data. All of the soft decision data values are stored in a high speed memory in real time. Subsequently non-coherent accumulated soft decision data is employed to detect the proper PN replica code. Logic selection means accesses the soft decision data stored in the high speed memory in non real time and selects the best estimate for the soft decision data and applies the soft decision data to a demodulator in non-real time to recover the hard data encoded in the received PN coded data.

Claims

1. Apparatus for acquiring and demodulating burst of long PN coded spread spectrum signals having known data bit symbol and chip times and length but no preamble synchronizing signals, comprising:

analog receiver means for receiving blocks of the long burst of PN coded signals and producing a digital output representative of a plurality of data bits defined by a larger plurality of chips,

correlator means N chips wide coupled to the output of said receiver means for producing a parallel partially despread block output N chips wide, where N is a small fractional part of the total number of chips in a data bit,

coherent accumulating means coupled to the output of said correlator means for producing in real time once each bit symbol time T_s a plurality N of preliminary soft decision data, at least one soft decision being indicative of the proper PN replica code alignment and the encoded bit of data received during the previous bit symbol time,

buffer storage mean coupled to the output of said coherent accumulation means for receiving and storing the soft decision data representative of the bursts of PN coded signals,

logic selection mean coupled to the buffer storage means for selecting relevant soft decision data indicative of the best estimate of the PN replica code and the encoded data,

said buffer storage means comprising means for determining the start of a burst of PN coded carrier signals, and

digital demodulation means coupled to the output of said logic selection means and to said means for determining the start of a burst of PN coded carrier signals for demodulating said soft decision data and producing a final hard best estimate data output.

2. Apparatus as set forth in claim 1 wherein the value of N is greater than the number of chips in the window of uncertainty.

3. Apparatus as set forth in claim 2 where the value N is between 20 and 2000 chips.

4. Apparatus as set forth in claim 3 wherein the number of chips in a bit symbol time is from 10 to 3000 times the value of N.

5. Apparatus as set forth in claim 1 wherein said digital demodulator means comprises a buffer memory for storing said best estimate of soft decision data for demodulation in non real time.

6. Apparatus as set forth in claim 5 which further includes processor means coupled to said logic selection means and said digital demodulator means for controlling the input of soft decision data to said demodulation means.

7. Apparatus as set forth in claim 6 which further includes PN replica generator means coupled to said processor means and said correlator means and wherein said processor means is adapted to control the output of said PN replica generator means.

8. Apparatus as set forth in claim 1 which further includes non-coherent accumulation means coupled to the output of said coherent accumulation means for generating a selection signal coupled to said logic selection means indicative of a condition in which a unique PN code is identifiable as a best estimate of the soft decision data.

9. Apparatus as set forth in claim 8 wherein said logic selection means includes means for selecting a plurality of soft decision data values and for reducing said plurality of soft decision data values to a unique best estimate soft decision value.

10. Apparatus as set forth in claim 9 wherein said means for selecting and reducing said soft decision data includes means for generating average values of soft decision data.

11. A method of rapidly acquiring long burst of PN coded spread spectrum signals having known data bit symbol times and chip times and length but having no preamble synchronizing signals, comprising the steps of:

receiving blocks of analog PN coded signals,

converting said blocks of analog signals to digital signals,

correlating said digital signals to provide a plurality N of multiplied and summed parallel partially despread soft decision data signals,

coherently accumulating said parallel partially despread signals over a symbol bit time to provide N soft decision values, where the value N is a fraction of the data bit symbol time in chips,

storing said N soft decision values in a high speed buffer memory,

non-coherently accumulating said N soft decision values over a plurality of bit symbol times to identify the start of the PN replica code,

selecting soft decision values from said high speed buffer memory indicative of the best estimate of the aligned PN replica code and a soft decision data value,

applying the selected soft decision values to logic means for reducing said plural of soft decision values to a unique soft decision value, and

demodulating the plurality of said unique soft decision values to provide a best estimate hard decision data output.