Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture

• US 5,414,820 A
• Filed: 03/21/1994
• Issued: 05/09/1995
• Est. Priority Date: 08/23/1991
• Status: Expired due to Term

• Current Assignee: Nexgen Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: Nexgen Incorporated (Advanced Micro Devices, Inc.)
• Inventors: McFarland, Harold L., Ho, Allen P.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/215,232
• Time in Patent Office: 414 Days
• Field of Search: 395/325, 395/275, 395/425, 395/200, 370/85.1, 340/825.5, 340/825.06, 340/825.07
• US Class Current: 710/307
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.

Claims

1. A bus interface unit for a computer system having at least a first bus and a second bus, wherein the architecture of said first bus supports coupling to a first bus master for generating a first bus transfer, said first bus transfer including an address, said architecture having a first bus control signal selectively indicating said first bus transfer is claimed by a device addressed by said address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus; and

control logic means, coupled to said first and second bus interface logic, for enabling a crossing transfer from said first bus to said second bus without waiting for assertion of said first bus control signal if said address of said first bus transfer is not mapped to one of said address regions that is associated with said first bus.

2. The bus interface unit of claim 1, wherein the architecture of said second bus has a passive protocol for terminating a bus transfer.

3. The bus interface unit of claim 1, wherein:

the architecture of said first bus has a multimaster arbitration protocol; and

said bus interface unit further comprises a buffer, coupled to said path, for storing said first bus transfer, such that said first bus can immediately perform other operations while said bus interface unit completes said crossing transfer on said second bus.

4. The bus interface unit of claim 1, wherein:

the architecture of said first bus has a multimaster arbitration protocol;

the architecture of said second bus has a passive protocol for terminating a bus transfer; and

said bus interface unit further comprises a buffer, coupled to said path, for storing said first bus transfer, such that said first bus can immediately perform other operations while said bus interface unit completes said crossing transfer on said second bus.

5. The bus interface unit of claim 1, wherein said address mapping logic includes a map RAM.

6. A bus interface unit for a computer system having at least a first bus and a second bus, wherein the architecture of said first bus has a multimaster arbitration protocol and supports coupling to a first bus master for generating a first bus transfer, said first bus transfer including an address, said architecture having a first bus control signal selectively indicating said first bus transfer is claimed by a device addressed by said address, and wherein said second bus has a passive protocol for terminating transfers on said second bus and supports coupling to a second bus master for generating a second bus transfer, said second bus transfer including a second address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus; and

control logic means, coupled to said first and second bus interface logic,

for enabling a first type of crossing transfer from said first bus to said second bus over said path if said first bus control signal is not asserted within a predefined waiting period after said first bus master initiates said first bus transfer, and

for enabling a second type of crossing transfer from said second bus to said first bus over said path if said second address of said second bus transfer is mapped to one of said address regions that is associated with said first bus.

7. The bus interface unit of claim 6, wherein at least some of said address regions have different block sizes among said regions.

8. The bus interface unit of claim 6, wherein said control logic means enables said first type of crossing transfer from said first bus to said second bus over said path without waiting for assertion of said first bus control signal if said address of said first bus transfer is not mapped to one of said address regions that is associated with said first bus.

9. The bus interface unit of claim 6, wherein said computer system includes I/O, conventional memory, and extended memory and wherein said plurality of address regions include separate address regions for said I/O, conventional memory, and extended memory.

10. The bus interface unit of claim 6, wherein said computer system includes I/O, conventional memory, and extended memory and wherein said plurality of address regions include separate addres regions for said I/O, conventional memory, and extended memory.

11. The bus interface unit of claim 6, wherein said address mapping logic includes a map RAM.

12. A bus interface unit for a computer system having at least a first bus and a second bus wherein said second bus has a passive protocol for terminating transfers on said second bus and supports coupling to a second bus master for generating a second bus transfer, said second bus transfer including a second address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus, said address regions including explicit memory ranges corresponding to video memory and BIOS extensions; and

control logic means, coupled to said first and second bus interface logic, for enabling a crossing transfer from said second bus to said first bus over said path if said second address of said second bus transfer is mapped to one of said address regions that is associated with said first bus.

13. The bus interface unit of claim 12, wherein said computer system includes I/O, conventional memory, and extended memory and wherein said plurality of address regions include separate address regions for said I/O, conventional memory, and extended memory.

14. The bus interface unit of claim 12, wherein said address mapping logic includes a map RAM.

15. A bus interface unit for a computer system having at least a first bus and a second bus, wherein said second bus has a passive protocol for terminating transfers on said second bus and supports coupling to a second bus master for generating a second bus transfer, said second bus transfer including a second address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus, said address regions differing in block size among said regions; and

control logic means, coupled to said first and second bus interface logic, for enabling a crossing transfer from said second bus to said first bus over said path if said second address of said second bus transfer is mapped to one of said address regions that is associated with said first bus.

16. The bus interface unit of claim 15, wherein said computer system includes I/O, conventional memory, and extended memory and wherein said plurality of address regions include separate addres regions for said I/O, conventional memory, and extended memory.

17. The bus interface unit of claim 15, wherein said address mapping logic includes a map RAM.

18. A bus interface unit for a computer system having at least a first bus and a second bus, wherein the architecture of said first bus has a multimaster arbitration protocol and supports coupling to a first bus master for generating a first bus transfer, said first bus including an address, said architecture having a first bus control signal selectively indicating said first bus transfer is claimed by a device addressed by said address, and wherein said second bus has a passive protocol for terminating transfers on said second bus and supports coupling to a second bus master for generating a second bus transfer, said second bus transfer including a second address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus;

control logic means, coupled to said first and second bus interface logic,

for enabling a first type of crossing transfer from said first bus to said second bus over said path if said first bus control signal is not asserted within a predefined waiting period after said first bus master initiates said first bus transfer, and

for enabling a second type of crossing transfer from said second bus to said first bus over said path if said second address of said second bus transfer is mapped to one of said address regions that is associated with said first bus; and

a buffer, coupled to said path, for storing said first bus transfer, such that said first bus can immediately perform other operations while said bus interface unit completes said first type of crossing transfer on said second bus.

19. The bus interface unit of claim 18, wherein said computer system includes I/O, conventional memory, and extended memory and wherein said plurality of address regions include separate address regions for said I/O, conventional memory, and extended memory.

20. A bus interface unit for a computer system having at least a first bus and a second bus, wherein the architecture of said first bus has a multimaster arbitration protocol and supports coupling to a first bus master for generating a first bus transfer, said first bus transfer including an address, said architecture having a first bus control signal selectively indicating said first bus transfer is claimed by a device addressed by said address, and wherein said second bus has a passive protocol for terminating transfers on said second bus and supports coupling to a second bus master for generating a second bus transfer, said second bus transfer including a second address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

a bidirectional path coupled between said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus;

control logic means, coupled to said first and second bus interface logic,

for enabling a first type of crossing transfer from said first bus to said second bus without waiting for assertion of said first bus control signal, if said address of said first bus transfer is not mapped to one of said address regions that is associated with said first bus, and

for enabling a second type of crossing transfer from said second bus to said first bus over said path if said second address of said second bus transfer is mapped to one of said address regions that is associated with said first bus; and

a buffer, coupled to said path, for storing said first bus transfer, such that said first bus can immediately perform other operations while said bus interface unit completes said first type of crossing transfer on said second bus.

21. The bus interface unit of claim 20, wherein said address mapping logic includes a map RAM.