Apparatus for serialization and deserialization of data, and resultant system for digital transmission of serial data

• US 5,414,830 A
• Filed: 07/09/1991
• Issued: 05/09/1995
• Est. Priority Date: 07/11/1990
• Status: Expired due to Term

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Marbot, Roland
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US07/727,429
• Time in Patent Office: 1,400 Days
• Field of Search: 395/800, 395/500, 395/550
• US Class Current: 710/71
• CPC Class Codes: G06F 7/76 Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

The apparatus 15 for serialization of words of N bits SYNC, OP, D0-D7 produces N clock signals CL0-CL9 of period T, delayed successively by T/N, to control respective registers (36, 38, 39) for the successive output of the bits of each word. An adder (40) reunites these bits in a serial data transmission signal (TS). The deserialization is applicable in particular to network transmission systems, and especially to information processing systems.

Claims

1. An apparatus (15) for serialization of words of N parallel bits comprising means (21) for simultaneously generating N clock signals (CL0-CL9) recurring at a period T and successively occurring with a delay of T/N therebetween, control circuit means (36, 38, 39) for receiving the N clock signals and responsive to the bits of each of said words for generating N output bits successively occurring at a rate corresponding to the occurrence of said N clock signals, and means (40) for serially arranging the N output bits issued from each of said words to form a serial signal (TS).

2. The apparatus of claim 1, wherein the control circuit means includes a buffer block (22) for memorization of the N parallel bits.

3. The apparatus of claim 1, wherein means (40) for serially arranging the N output bits includes a tree of EXCLUSIVE-OR gates (41).

4. The apparatus of claim 1, wherein said control circuit means includes a number of registers N that respectively receive the N parallel bits and the N clock signals.

5. The apparatus of claim 4, wherein the N registers comprise registers for encoding the respective N parallel bits.

6. The apparatus of claim 5, wherein a signal input of each register is provided to an output of an EXCLUSIVE-OR gate (37) having one input receiving one of the N parallel bits and another input connected to an output of the register.

7. An apparatus (19) for deserialization of words of N serial bits comprising means (42) for simultaneously generating N clock signals (CL0-CL9) recurring at a period T and successively occurring with a delay of T/N therebetween, and control means (69) responsive to at least a predetermined number n of the N clock signals to provide a parallel output corresponding to a respective number n of bits of each of the words.

8. The apparatus of claim 7, and further comprising means (20) for putting n bits of the parallel output in the same order as that transmitted.

9. The apparatus of claim 7, wherein the control means includes the number n of registers receiving said respective n bits of each word and controlled by the respective n clock signals.

10. The apparatus of claim 9, wherein the registers comprise means for decoding respective bits.

11. The apparatus of claim 9, wherein the control means includes EXCLUSIVE-OR gates (70) each having one input connected to the output of a register and another input connected to the output of a preceding register.

12. A system (10) for digital data transmission, including a transmitter (12) using a clock signal (CL) recurring at a period T and a parallel input signal (DS), said transmitter including a serializer (15) and an encoder to transmit a serial signal (TS) at a transmission rate R, and a receiver (13) connected to receive the serial signal and including a clock recuperator (18) for recovering the clock signal from the serial signal, a deserializer (19) and a decoder to supply a parallel output signal Dout wherein the period T of the clock signal is a multiple N of the transmission rate R and wherein at least one of the serializer and deserializer includes means for simultaneously generating N clock signals recurring at a period T and succesively occurring with a delay of T/N therebetween.

13. The system of claim 12, wherein the deserializer includes means for generating N clock signals recurring at the period T and successively occurring with a delay of T/N therebetween, and further wherein said clock recuperator comprises said means for generating N clock signals.