Power control staggering circuit for powering different components at different delay timings

• US 5,414,863 A
• Filed: 04/02/1993
• Issued: 05/09/1995
• Est. Priority Date: 04/02/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Lee, Robert H. J., Kenny, John D.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/041,456
• Time in Patent Office: 767 Days
• Field of Search: 395/750, 364/707, 364/492, 307/603, 307/606, 307/64, 307/141, 307/141.4, 340/825.06, 340/825.22, 370/112, 370/108, 318/445, 318/484
• US Class Current: 713/330
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

A power control circuit for a device such as a personal computer, including a laptop or notebook computer, which can conserve battery use, prevent power surges to promote longer battery charges and longer battery life, and can assure that circuitry is correctly biased. The power control circuitry of the present invention achieves these objectives by appropriately staggering the powering on of circuit components of the computer. A circuit for achieving these objectives may feature at least one memory for storing power control state data and a multiplexer for receiving the power control state data stored in the at least one memory. Further, a plurality of serially connected power control output circuits connected to the multiplexer output power control signals based on the power control state data stored in the at least one memory. A first of the plurality of serially connected power control output circuits has a minimum delay and each succeeding of the plurality of serially connected power control output circuits has an increasing delay.

Claims

1. A power control apparatus for controlling an application of power control signals to a plurality of components to be powered, comprising:

at least one memory for storing power control state data;

a multiplexer for receiving the power control state data stored in the at least one memory; and

a plurality of serially connected power control outputs connected to the multiplexer for outputting the power control signals based on the power control state data stored in the at least one memory, and wherein a first of the plurality of serially connected power control outputs has a minimum delay and each succeeding of the plurality of serially connected power control outputs has an increasing delay.

2. The power control apparatus according to claim 1, wherein a first of the plurality of serially connected power control outputs comprises a flip-flop and each succeeding of the plurality of serially connected power control outputs comprises a delay circuit and a flip-flop.

3. The power control apparatus according to claim 2, wherein the at least one memory comprises at least one register.

4. The power control apparatus according to claim 1, wherein the at least one memory comprises at least one register.

5. A power control apparatus for controlling an application of power control signals to a plurality of components to be powered, comprising:

at least one memory means for storing power control state data;

a multiplexer means for receiving the power control state data stored in the at least one memory means; and

a plurality of serially connected power control output means connected to the multiplexer means for outputting the power control signals based on the power control state data stored in the at least one memory means, and wherein a first of the plurality of serially connected power control output means has a minimum delay and each succeeding of the plurality of serially connected power control output means has an increasing delay.

6. The power control apparatus according to claim 5, wherein a first of the plurality of serially connected power control output means comprises a flip-flop and each succeeding of the plurality of serially connected power control output means comprises a delay means and a flip-flop.

7. The power control apparatus according to claim 6, wherein the at least one memory means comprises at least one register.

8. The power control apparatus according to claim 5, wherein the at least one memory means comprises at least one register.