Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer
First Claim
1. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:
- epitaxially depositing a layer of silicon on a surface of a sapphire substrate;
implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;
maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°
C.) such that said temperature is substantially uniform throughout said layer of silicon during said ion implanting step; and
annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed.
6 Assignments
0 Petitions
Accused Products
Abstract
A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.
Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.
Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. |Vtn |=|Vtp |).
-
Citations
15 Claims
-
1. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:
-
epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°
C.) such that said temperature is substantially uniform throughout said layer of silicon during said ion implanting step; andannealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:
-
epitaxially depositing a layer of silicon on a surface of a sapphire substrate; positioning said sapphire substrate adjacent a chamber through which flows a coolant such that said coolant contacts said sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; controlling the flow rate or the temperature or both the flow rate and the temperature of said coolant through said chamber to maintain said layer of silicon substantially at or below a temperature of approximately zero degree centigrade (0°
) during said ion implanting step; andannealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed. - View Dependent Claims (14, 15)
-
Specification