Apparatus and method for testing circuit board interconnect integrity

• US 5,416,409 A
• Filed: 09/08/1993
• Issued: 05/16/1995
• Est. Priority Date: 03/23/1992
• Status: Expired due to Fees

• Current Assignee: Ministor Peripherals International Limited
• Original Assignee: Ministor Peripherals International Limited
• Inventors: Hunter, Paul W.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US08/117,956
• Time in Patent Office: 615 Days
• Field of Search: 324/158 R, 324/537, 324/73.1, 324/158.1, 324/500, 371/15.1, 371/22.3, 371/22.6, 371/25.1
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2815 Functional tests, e.g. boundary scans, using the normal I/O contacts contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence

Abstract

Apparatus for testing the integrity of a plurality of conductive circuit connection paths between output pins on a first integrated circuit and input pins on a second integrated circuit on a circuit board includes first boundary scan cells associated with each output pin on the first integrated circuit, each of the first boundary scan cells adapted to selectively place a data test bit loaded therein onto the one of the output pins with which it is associated, second boundary scan cells associated with each input pin on the second one of the integrated circuits, each of the second boundary scan cells adapted to selectively store the digital value present on the one of the input pins with which it is associated, a controller for loading a data test bit into each of the boundary scan cells associated with each output pin on the first one of the integrated circuits, for respectively placing each of the data test bits onto respective ones of the output pins of the first integrated circuit, for selectively storing into each of the second boundary scan cells in the second integrated circuit the digital values present on the ones of the input pins associated therewith, and for comparing the digital values with the data test bits. Apparatus for observing circuit nodes in an analog integrated circuit includes a multiplexer connected to a plurality of circuit nodes to be observed, a sample/hold circuit for holding voltages obtained from the selected nodes, and a controller responsive to external signals for controlling the operation of the multiplexer and the sample/hold circuit.

Claims

1. In a circuit board assembly comprising a plurality of integrated circuits disposed on a circuit board, said circuit board including a plurality of conductive circuit connection paths between output pins of a first one of said integrated circuits and input pins of a second one of said integrated circuits, apparatus for testing the integrity of said plurality of conductive circuit connection paths, including:

a first boundary scan cell associated with each output pin on the first one of the integrated circuits, each of said first boundary scan cell adapted to selectively place a data test bit loaded therein onto the one of the output pins with which it is associated;

a second boundary scan cell associated with each input pin on the second one of the integrated circuits, each of said second boundary scan cell adapted to selectively store a logic value present on the one of the input pins with which it is associated;

a controller, disposed on the circuit board assembly, for loading a data test bit into each of said first boundary scan cell associated with each output pin on the first one of the integrated circuits, for respectively placing each of said data test bits onto respective ones of the output pins of the first integrated circuit, for selectively loading into each of said second boundary scan cell in the second integrated circuit the logic values present on the ones of the input pins associated therewith, and for comparing said logic values with said data test bits.

2. An analog integrated circuit including:

one or more analog function circuits disposed in a circuit portion of said integrated circuit, said one or more analog function circuits each including one or more circuit nodes, each of said circuit nodes characterized by the presence of a characteristic voltage when said integrated circuit is properly connected and said function circuit is properly operating;

an analog multiplexer having a plurality of analog inputs, an analog output, and at least one control input, each of said analog inputs connected to a different one of said circuit nodes through a buffer;

a sample/hold amplifier having a sample input connected to the output of said analog multiplexer, an output, and a control input;

a controller, having one or more inputs, and having a first at least one output connected to the at least one control input of said analog multiplexer, and a second output connected to the control input of said sample/hold amplifier, said controller responsive to signals from outside said integrated circuit for controlling said analog multiplexer and said sample/hold amplifier.

3. The integrated circuit of claim 2, further including;

a three-state buffer amplifier having an input connected to the output of said sample/hold amplifier, an output connected directly or indirectly to an output pin of said integrated circuit and a three-state control input; and

said controller further including a third output connected to the three-state control input of said three-state buffer amplifier, and wherein said signals from outside said integrated circuit also control said three-state buffer amplifier.

4. The integrated circuit of claim 2 further including:

an additional analog circuit node in said analog integrated circuit, said additional circuit node characterized by the presence of a stable-voltage-convertible characteristic analog parameter thereon when said function circuit is properly connected and operating; and

signal-conditioning means connected between said additional circuit nodes and one of said analog inputs to said analog multiplexer, said signal-conditioning means configured to convert said analog parameter to a stable voltage.

5. The integrated circuit of claim 4, wherein said signal-conditioning means comprises an integrator circuit.

6. A diagnostic architecture for analyzing the functioning of a plurality of analog integrated circuits, said architecture comprising:

a plurality of analog integrated circuits, each of said analog integrated circuits comprising one or more analog function circuits disposed in a circuit portion of said integrated circuit, said one or more analog function circuits each including one or more circuit nodes, each of said circuit nodes characterized by the presence of a characteristic analog voltage when said function circuit is property connected and operating;

an analog multiplexer having a plurality of analog inputs, an analog output, and at least one control input, each of said analog inputs connected to a different one of said circuit nodes through a buffer;

a sample/hold amplifier having a sample input connected to the output of said analog multiplexer, an output, and a control input;

a three-state buffer amplifier having an input connected to the output of said sample/hold amplifier, an output connected directly or indirectly to an output pin of said integrated circuit, and a three-state control input; and

a controller, having one or more inputs, and having a first at least one output connected to the at least one control input of said analog multiplexer, a second output connected to the control input of said sample/hold amplifier, and a third output connected to the three-state control input of said three-state buffer amplifier, said controller responsive to test command signals from outside said integrated circuit, for controlling said analog multiplexer, said sample/hold amplifier, and said three-state buffer amplifier;

a common analog signal line connected to the outputs of the three-state buffer amplifiers of each of said analog integrated circuits;

an A/D converter having an analog input connected to said common analog signal line, and a digital output bus for presenting digital output data representing said analog parameters;

controller means, coupled to said plurality of analog integrated circuits and to said A/D converter, for providing said test command signals to each of said analog integrated circuits, for obtaining digital output data from said A/D converter, and for comparing said digital output data with expected values.

7. The diagnostic architecture of claim 6 further including:

an additional analog circuit node in at least one of said analog integrated circuits, said additional circuit node characterized by the presence of a stable-voltage-convertible characteristic analog parameter thereon when said function circuit is properly connected and operating; and

signal-conditioning means connected between said additional circuit nodes and one of said analog inputs to said analog multiplexer, said signal-conditioning means configured to convert said analog parameter to a stable voltage.

8. The diagnostic architecture of claim 7, wherein said signal-conditioning means comprises an integrator circuit.

9. A diagnostic architecture for analyzing the functioning of an analog integrated circuit, said architecture comprising:

an analog integrated circuit, said analog integrated circuit comprising one or more analog function circuits disposed in a circuit portion of said integrated circuit, said one or more analog function circuits each including one or more circuit nodes, each of said circuit nodes characterized by the presence of a characteristic analog voltage when said function circuit is properly connected and operating;

an analog multiplexer having a plurality of analog inputs, an analog output, and at least one control input, each of said analog inputs connected to a different one of said circuit nodes through a buffer;

a sample/hold amplifier having a sample input connected to the output of said analog multiplexer, a control input, and an output connected directly or indirectly to an output pin of said integrated circuit; and

a controller, having one or more inputs, and having a first at least one output connected to the at least one control input of said analog multiplexer, and a second output connected to the control input of said sample/hold amplifier, said controller responsive to test command signals from outside said integrated circuit, for controlling said analog multiplexer, and said sample/hold amplifier;

an A/D converter having an analog input connected to said output pin, and a digital output bus for presenting digital output data representing said analog parameters;

a controller, coupled to said analog integrated circuit and to said A/D converter, for providing said test command signals to said analog integrated circuit, for obtaining digital output data from said A/D converter, and for comparing said digital output data with expected values.

10. The diagnostic architecture of claim 9 further including:

an additional analog circuit node in said analog integrated circuits, said additional circuit node characterized by the presence of a stable-voltage-convertible characteristic analog parameter thereon when said function circuit is properly connected and operating; and

a signal-conditioner connected between said additional circuit node and one of said analog inputs to said analog multiplexer, said signal-conditioning means configured to convert said analog parameter to a stable voltage.

11. The diagnostic architecture of claim 10, wherein said signal-conditioner comprises an integrator circuit.

12. A method for analyzing the functioning of an analog circuit including the steps of:

a) generating, from a controller resource, signals to be placed in an analog scan controller;

b) generating, from said analog scan controller, signals in response to said signals from said controller resource to be placed onto a control line of a multiplexer, and a sample/hold circuit, a signal from said sample/hold circuit being placed in an analog-to-digital converter;

c) generating, from said controller resource, a signal to said analog-to-digital converter to perform a conversion of said signal from said sample/hold circuit; and

d) comparing, in said controller resource, a converted signal from said analog-to-digital converter to an expected value.

13. The method of claim 12, further including the step of:

a1) presenting a stable-voltage convertible characteristic analog parameter to said analog circuit.

14. A method for analyzing the functioning of a plurality analog circuits including the steps of:

a) generating, from a controller resource, signals to be placed in an analog scan controller;

b) generating, from said analog scan controller, signals in response to said signals from said controller resource to be placed onto a control line of a multiplexer, a sample/hold circuit, and a three-state buffer;

c) placing a signal from said three-state buffer in an analog-to-digital converter;

d) generating, from said controller resource, a signal to said analog-to-digital converter to perform a conversion of said signal from said three-state buffer; and

e) comparing, in said controller resource, a converted signal from said analog-to-digital converter to an expected value.

15. The method of claim 14, further including the step of:

a1) presenting a stable-voltage convertible characteristic analog parameter to said plurality of analog circuits.