Adaptive clock generation with pseudo random variation

• US 5,416,434 A
• Filed: 03/05/1993
• Issued: 05/16/1995
• Est. Priority Date: 03/05/1993
• Status: Expired due to Term

• Current Assignee: Koninklijke Philips N.V.
• Original Assignee: HP Inc.
• Inventors: Kootstra, Steve, Powers, Daniel J.
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): Riley, Shawn
• Application Number:
  US08/026,716
• Time in Patent Office: 802 Days
• Field of Search: 307/265, 307/268, 328/28, 328/63, 328/72, 328/74, 395/550, 395/600, 395/650, 364/254.8, 364/260.2, 364/270.8
• US Class Current: 327/113
• CPC Class Codes: H03K 3/72 with means for varying repetition rate of trains
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

Adaptive clock generator including a master clock. A control means detects the current operating mode and, in response, provides a corresponding integer output N. A programmable pulse generator provides an output clock signal comprising a "high" pulse having a predetermined width followed by a "low" pulse having a width of N master clock periods. A dithered clock signal may be provided when the control means provides an integer output N selected from a set of integer values. Preferably, N is selected in a random or pseudo-random manner.

Claims

1. A method in an adaptive clock generating system for providing an adaptive clock signal to a digital circuit having a processor and memory, said method comprising the steps of:

initializing said adaptive clock signal to operate at a first clock frequency;

determining that said processor is accessing said memory;

decreasing said first clock frequency to a second clock frequency in response to said determining step;

returning to said first clock frequency when said memory is no longer being accessed;

detecting that said processor is processing an interrupt routine;

increasing said first clock frequency to a third clock frequency in response to said detecting step; and

returning to said first clock frequency when said interrupt routine has been processed.

3. The adaptive clock generating system of claim 1, wherein said first clock frequency varies in a pseudo-random manner to reduce the average radiated energy from said adaptive clock generating system.

2. An adaptive clock generating system for providing an adaptive clock signal to a digital circuit having a processor and memory, said system comprising:

means for initializing said adaptive clock signal to operate at a first clock frequency;

means for determining that said processor is accessing said memory;

means for decreasing said first clock frequency to a second clock frequency in response to said determining means;

means for returning to said first clock frequency when said memory is no longer being accessed;

means for detecting that said processor is processing an interrupt routine;

means for increasing said first clock frequency to a third clock frequency in response to said detecting step; and

means for returning to said first clock frequency when said interrupt routine has been processed.

4. The adaptive clock generating system of claim 2, wherein said first clock frequency varies in a pseudo-random manner to reduce the average radiated energy from said adaptive clock generating system.