Circuit design support system and circuit producing method

• US 5,416,718 A
• Filed: 09/03/1992
• Issued: 05/16/1995
• Est. Priority Date: 09/05/1991
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamazaki, Masami
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US07/940,278
• Time in Patent Office: 985 Days
• Field of Search: 364/488, 364/490, 364/491, 364/578, 395/919, 395/920, 395/921, 395/922, 395/923
• US Class Current: 716/102
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: Y10S 706/921 Layout, e.g. circuit, construction

Abstract

In a circuit design support system, a logic minimizing unit receives data indicating a functional specification of a desired circuit and minimizes logical sequences of the desired circuit. A cell assignment unit assigns cells to each of minimized logical sequences determined by the logic minimizing unit and generates data on a circuit configuration of the desired circuit. The cells are logic units. A load/timing check unit receives the data on the circuit configuration and simultaneously executes a load check and a timing check. The load check determines whether or not the circuit configuration has a load driving ability within a tolerable load driving ability. The timing check determines whether or not the circuit configuration has a delay time of a signal within a tolerable delay time. A load adjustment unit executes a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of the circuit configuration falls within the tolerable driving ability. A timing adjustment unit executes a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of the circuit configuration falls within the tolerable delay time.

Claims

1. A circuit design support system comprising:

logic minimizing means for receiving data indicating a functional specification of a desired circuit and for minimizing logical sequences of the desired circuit;

cell assignment means, operatively coupled to said logic minimizing means, for assigning cells to each of minimized logical sequences determined by said logic minimizing means and for generating data on a circuit configuration of the desired circuit;

load/timing check means, operatively coupled to said cell assignment means, for receiving the data on the circuit configuration and for simultaneously executing a load check and a timing check, said load check determining whether or not the circuit configuration has a load driving ability within a tolerable load driving ability, said timing check determining whether or not the circuit configuration has a delay time of a signal within a tolerable delay time, said load/timing signal check means comprising means for determining whether or not a signal output terminal in the circuit configuration has an overload and for calculating a delay time of a signal path including said signal output terminal assuming that a tolerable load is connected to said signal output terminal;

load adjustment means, operatively coupled to said load/timing check means, for executing a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of said circuit configuration falls within the tolerable driving ability; and

timing adjustment means, operatively coupled to said load/timing check means, for executing a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of said circuit configuration falls within the tolerable delay time.

2. A circuit design support system as claimed in claim 1, wherein:

said load/timing check means comprises first means for identifying critical signal paths in the circuit configuration, said critical signal paths respectively having delay times exceeding the tolerable delay time; and

said load adjustment means comprises second means for executing the load adjustment so that delay times of the critical signal paths are reduced.

3. A circuit design support system as claimed in claim 1, wherein:

said load/timing check means comprises first means for identifying critical signal paths in the circuit configuration, said critical signal paths respectively having delay times exceeding the tolerable delay time; and

said load adjustment means comprises second means for inserting buffer elements in signal paths other than the critical signal paths so that so that delay times of the critical signal paths are reduced.

4. A circuit producing method comprising the steps of:

(a) receiving data indicating a functional specification of a desired circuit and minimizing logical sequences of the desired circuit;

(b) assigning cells to each of minimized logical sequences determined by said step (a) and generating data on a circuit configuration of the desired circuit;

(c) receiving the data on the circuit configuration and simultaneously executing a load check and a timing check, said load check determining whether or not the circuit configuration has a load driving ability within a tolerable load driving ability, said timing check determining whether or not the circuit configuration has a delay time of a signal within a tolerable delay time;

(d) executing a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of said circuit configuration falls within the tolerable driving ability; and

(e) executing a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of said circuit configuration falls within the tolerable delay time.

5. A method as claimed in claim 4, wherein said step (c) comprises the steps of:

determining whether or not a signal output terminal in the circuit configuration has an overload; and

calculating a delay time of a signal path including said signal output terminal assuming that a tolerable load is connected to said signal output terminal.

6. A method as claimed in claim 4, wherein:

said step (c) comprises the step of identifying critical signal paths in the circuit configuration, said critical signal paths respectively having delay times exceeding the tolerable delay time; and

said step (d) comprises the step of executing the load adjustment so that delay times of the critical signal paths are reduced.

7. A method as claimed in claim 4, wherein:

said step (c) comprises the step of identifying critical signal paths in the circuit configuration, said critical signal paths respectively having delay times exceeding the tolerable delay time; and

said step (d) comprises the step of inserting buffer elements in signal paths other than the critical signal paths so that so that delay times of the critical signal paths are reduced.