Method and apparatus for optimizing block shape in hierarchical IC design
First Claim
1. A computer implemented method of optimizing the shapes of blocks on an integrated circuit chip wherein blocks Ai (i=1,2, . . . ,k) are placed in an area A on the integrated circuit chip in a non-slicing configuration on the chip, at least some of the blocks having variable shapes, the method comprising the steps of:
- using computer means to;
perform, with respect to at least one block having a variable shape, a step of varying the shape thereof by randomly performing one of the steps of (a) increasing a selected value for the width of a block Ai (i=1,2, . . . ,k), and (b) increasing a selected value for the height of the block;
then, to evaluate one of (a) the area size and width of the area and (b) the area size and height of the area A after the performing step;
to accept or reject the increase of (a) or (b) in accordance with the evaluation;
to determine a relation between a shape of the area A and shapes of the blocks Ai (i=1,2, . . . ,k) in the area A on the basis of the previously mentioned steps; and
to determine a combination of optimal block shapes by use of the shape relation.
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Abstract
A whole process is divided into a rough floor plan and a detailed floor plan. In the rough floor plan, locations and shapes of blocks are roughly determined. In the detailed floor plan; an estimation of shapes of shape-variable blocks and sizes of wiring areas between blocks is simplified by listing all of slicing structures and optimizing block shapes for respective channel structures without greatly changing a block placement and pin locations. A combination of a hierarchical technique and a heuristic technique is used to allow block shapes to be optimized by selecting only suitable channel structures without listing all of an exponential number of the channel structures. In this way, the block shape optimization is simplified. The time spent in the simplified block shape optimization generally has a linear order with respect to the number of the blocks.
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Citations
22 Claims
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1. A computer implemented method of optimizing the shapes of blocks on an integrated circuit chip wherein blocks Ai (i=1,2, . . . ,k) are placed in an area A on the integrated circuit chip in a non-slicing configuration on the chip, at least some of the blocks having variable shapes, the method comprising the steps of:
using computer means to; perform, with respect to at least one block having a variable shape, a step of varying the shape thereof by randomly performing one of the steps of (a) increasing a selected value for the width of a block Ai (i=1,2, . . . ,k), and (b) increasing a selected value for the height of the block; then, to evaluate one of (a) the area size and width of the area and (b) the area size and height of the area A after the performing step; to accept or reject the increase of (a) or (b) in accordance with the evaluation; to determine a relation between a shape of the area A and shapes of the blocks Ai (i=1,2, . . . ,k) in the area A on the basis of the previously mentioned steps; and to determine a combination of optimal block shapes by use of the shape relation.
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2. A computer implemented method of optimizing shapes of blocks including standard cells in a block placement of a slicing channel structure on a semiconductor chip, at least some of the blocks having variable shapes, comprising the steps of using a computer means for:
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preliminarily positioning unit size representations of the blocks; estimating final shapes of the blocks; listing a plurality of different slicing channel structures, less than all possible slicing channel structures, in accordance with the estimated final shapes of the blocks; providing optimal block shapes for each listed structure; and selecting an optimal configuration of blocks for placement on the semiconductor chip. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer implemented method of optimizing shapes of blocks including standard cells in a block placement of a slicing channel structure on a semiconductor chip, at least some of the blocks having variable shapes, comprising the steps of:
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preliminarily positioning unit size blocks; and providing optimal block shapes for said unit size blocks to minimize a resultant chip size, wherein said step of providing optimal block shapes comprises eliminating dead space on the chip by varying a shape of at least one block Ai (i=1,2, . . . ,k) having a variable shape, by randomly performing one of the steps of (a) increasing a selected value for a width of said at least one block, and (b) increasing a selected value for a height of said at least one block, thereby repeatedly changing an aspect ratio of said at least one block to eliminate dead space on the chip. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification