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Method and apparatus for optimizing block shape in hierarchical IC design

  • US 5,416,720 A
  • Filed: 07/08/1994
  • Issued: 05/16/1995
  • Est. Priority Date: 04/21/1988
  • Status: Expired due to Term
First Claim
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1. A computer implemented method of optimizing the shapes of blocks on an integrated circuit chip wherein blocks Ai (i=1,2, . . . ,k) are placed in an area A on the integrated circuit chip in a non-slicing configuration on the chip, at least some of the blocks having variable shapes, the method comprising the steps of:

  • using computer means to;

    perform, with respect to at least one block having a variable shape, a step of varying the shape thereof by randomly performing one of the steps of (a) increasing a selected value for the width of a block Ai (i=1,2, . . . ,k), and (b) increasing a selected value for the height of the block;

    then, to evaluate one of (a) the area size and width of the area and (b) the area size and height of the area A after the performing step;

    to accept or reject the increase of (a) or (b) in accordance with the evaluation;

    to determine a relation between a shape of the area A and shapes of the blocks Ai (i=1,2, . . . ,k) in the area A on the basis of the previously mentioned steps; and

    to determine a combination of optimal block shapes by use of the shape relation.

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