Vertical field-effect transistor and a semiconductor memory cell having the transistor

• US 5,416,736 A
• Filed: 07/25/1994
• Issued: 05/16/1995
• Est. Priority Date: 07/28/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kirsch, Howard C., Kosa, Yasunobu
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/279,963
• Time in Patent Office: 295 Days
• Field of Search: 365/174, 365/188, 257/381, 257/904, 257/380, 437/48, 437/52
• US Class Current: 365/174
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

Claims

1. A static random access memory cell comprising:

a semiconductor substrate having a first conductivity type;

a first latch transistor that lies at least in part over the substrate and within a trench, wherein;

the trench has a bottom, a top, and a wall;

the trench contacts a first doped region, extends through a first semiconductor layer, and extends through a second doped region;

the first doped region lies within the substrate;

the first doped region has a second conductivity that is opposite the first conductivity type;

a portion of the first doped region that lies at the wall of the trench acts as a source region for the first latch transistor;

the first semiconductor layer overlies the first doped region, wherein;

the first semiconductor layer has the first conductivity type;

the first semiconductor layer has a first surface and a second surface that lies on an opposite side of the first semiconductor layer;

the first doped region lies adjacent to the first surface; and

a portion of the first semiconductor layer lies at the wall of the trench, overlies the portion of the first doped region that lies at the wall of the trench, and acts as a channel region for the first latch transistor;

the second doped region lies within the first semiconductor layer adjacent to the second surface;

the second doped region has the first conductivity type;

a portion of the second doped region lies at the wall of the trench, overlies the portion of the first semiconductor layer that lies at the wall of the trench, and acts as a drain region for the first latch transistor;

a first gate dielectric layer lying adjacent to the wall and bottom of the trench; and

a first conductive member adjacent to the first gate dielectric layer;

a patterned insulating layer overlying the first semiconductor layer and the first conductive member, wherein;

the patterned insulating layer includes a first insulating layer opening having a bottom, a top, and a wall; and

the first insulating layer opening overlies the first semiconductor layer and none of the first insulating layer opening overlies the trench; and

a first load transistor that includes;

a second semiconductor layer having the second conductivity type and lying along the bottom and wall of the first insulating layer opening and over a portion of the patterned insulating layer, wherein the second semiconductor layer includes;

doped portions that lie along the bottom of the first insulating layer opening, near the top of the first insulating layer opening, and overlying the patterned insulating layer, wherein;

the doped portions have the first conductivity type;

one of the doped portions of the second semiconductor layer that lies along the bottom of the first insulating layer opening acts as a drain region for the first load transistor; and

another doped portion of the second semiconductor layer overlies the top of the first insulating layer opening and acts as a source region for the first load transistor;

a wall portion of the second semiconductor layer lies along the wall and between the bottom and the top of the first insulating layer opening, wherein the wall portion of the second semiconductor layer acts as a channel region for the first load transistor;

a second gate dielectric layer lying adjacent to the second semiconductor layer;

a second conductive member that lies adjacent to the second gate dielectric layer.

2. The memory cell of claim 1, wherein the memory cell further comprises:

a second latch transistor similar to the first latch transistor;

a second load transistor similar to the first load transistor; and

a first pass transistor and a second pass transistor that are n-channel planar field-effect transistors each having a channel region within the first semiconductor layer, wherein each pass transistor has a first source/drain region, a second source/drain region, and a gate electrode.

3. The memory cell of claim 2, wherein:

the source regions of the first and second load transistors are electrically connected to one another;

the source regions of the first and second latch transistors are part of the first doped region; and

the first pass transistor has its first source/drain region electrically connected to a first bit line, the second pass transistor has its first source/drain region electrically connected to a second bit line, and gate electrodes of the pass transistors are part of a word line.

4. The memory cell of claim 3, wherein:

the first pass, first latch, and first load transistors are associated with a first storage node and the second pass, second latch, and second load transistors are associated with a second storage node;

the drain region of the first latch transistor, the drain region of the first load transistor, the second source/drain region of the first pass transistor, a gate electrode for the second latch transistor, and a gate electrode for the second load transistor are electrically connected to one another; and

the drain region of the second latch transistor, the drain region of the second load transistor, the second source/drain region of the second pass transistor, a gate electrode for the first latch transistor, and a gate electrode for the first load transistor are electrically connected to one another.

5. The memory cell of claim 1, wherein the first latch transistor and the first load transistor are at different elevations.

6. The memory cell of claim 1, further comprising a conductive barrier layer, wherein the conductive barrier layer:

lies between the second doped region of the first latch transistor and the one of the doped portions of the second semiconductor layer of the first load transistor; and

is part of an electrical connection between the second doped region of the first latch transistor and the one of the doped portions and virtually prevents dopant migration between the second doped region of the first latch transistor and the one of the doped portions.

11. The memory cell of claim 1, wherein the first latch transistor further comprises

a third doped region, wherein:

the third doped region lies adjacent to the top and wall of the trench;

the third doped region has the second conductivity type; and

a combination of the second and third doped regions is a graded diffusion junction.

7. A static random access memory cell comprising:

a first doped region within a semiconductor substrate, wherein the first doped region has a first conductivity type and the substrate has a second conductivity type that is opposite the first conductivity type;

a first silicon layer overlying the first doped region, wherein;

the first silicon layer has the second conductivity type;

the first silicon layer has a first surface and a second surface that lies on an opposite side of the first silicon layer; and

the first doped region lies adjacent to the first surface;

a first pass transistor and a second pass transistor, each pass transistor includes;

a first gate dielectric layer overlying the first silicon layer;

a first conductive member overlying the first gate dielectric layer;

portions of second and third doped regions lying adjacent to the second surface of the first silicon layer and on opposite sides of the first conductive member, wherein;

the second and third doped regions have the first conductivity type; and

a channel region that lies adjacent to the second surface of the first silicon layer and between the second and third doped regions;

a first latch transistor and a second latch transistor lying at least in part within trenches, wherein;

each of the trenches has a bottom, a top, and a wall, and extends through one of the second doped regions, extends through the first silicon layer and contacts the first doped region;

portions of the first doped region lie at the walls of the trenches and act as source regions for the latch transistors;

portions of the first silicon layer lie at the walls of the trenches, overlie the portions of the first doped regions that lie at the walls of the trenches, and act as channel regions for the latch transistors;

portions of the second doped regions lie at the walls of the trenches, overlie the portions of the first silicon layer that lie at the walls of the trenches, and act as drain regions for the latch transistors;

a second gate dielectric layer lies adjacent to the walls and bottoms of the trenches;

second conductive members lie adjacent to portions of the second gate dielectric layer;

a patterned insulating layer over the first silicon layer and the second conductive members, wherein;

the patterned insulating layer includes first insulating layer openings and second insulating layer openings,

each of the first insulating layer openings has a bottom, a top, and a wall; and

all of each first insulating layer opening overlies the first silicon layer and none of each first insulating layer opening overlies any of the trenches; and

each of the second insulating layer openings extends to one of the second conductive members; and

a first load transistor and a second load transistor, wherein the load transistors include;

portions of a second silicon layer having the first conductivity type, wherein the portions of the second silicon layer lie along the bottoms and walls of the first insulating layer openings and over a portion of the patterned insulating layer;

doped portions of the second silicon layer that lie along the bottom of each first insulating layer opening, near the top of each first insulating layer opening, and over the patterned insulating layer, wherein the doped portions;

have the second conductivity type;

that lie along the bottoms of the first insulating layer openings act as drain regions for the load transistors; and

that overlie the tops of the first insulating layer openings act as source regions for the load transistors;

wall portions of the second silicon layer lie along the walls and between the bottom and the top of each first insulating layer opening, wherein the wall portions of the second silicon layer act as channel regions for the load transistors;

a third gate dielectric layer adjacent the portions of the second silicon layer lying within the first insulating layer openings;

third conductive members that are each adjacent that portion of the third gate dielectric layer, wherein;

one of the third conductive members acts as a gate electrode for the first load transistor, lies within one of the second insulating layer openings, and is part of an electrical connection to the second conductive member that acts as a gate electrode for the first latch transistor;

another one of the third conductive members acts as a gate electrode for the second load transistor, lies within another one of the second insulating layer openings, and is part of an electrical connection to the second conductive member that acts as a gate electrode for the second latch transistor.

8. The memory cell of claim 7, wherein the second conductive members comprises a conductive barrier layer, wherein the conductive barrier layer:

lies between the drain regions of the latch transistors and the drain regions of the load transistors;

is part of an electrical connection between the drain regions of the first latch and first load transistors and virtually prevents dopant migration between the drain regions of first latch and first load transistors; and

is part of an electrical connection between the drain regions of the second latch and second load transistors and virtually prevents dopant migration between the drain regions of second latch and second load transistors.

12. The memory cell of claim 7, wherein the first latch and second latch transistors further comprise fourth doped regions, wherein:

the fourth doped regions lie adjacent to the tops and walls of the trenches;

the fourth doped regions have the second conductivity type; and

combinations of the second and fourth doped regions are graded diffusion junctions.

9. A semiconductor device comprising:

a patterned insulating layer overlying a semiconductor substrate, wherein;

the patterned insulating layer includes an insulating layer opening with a top, a bottom, and a wall;

the insulating layer opening has an insulating layer opening width;

a vertical thin-film field-effect transistor including;

a masking layer including a masking layer opening over the insulating layer, wherein;

the masking layer opening overlies the insulating layer opening;

the masking layer opening has a masking layer opening width that is narrower than the insulating layer opening width;

a semiconductor layer having a first conductivity type overlying the masking layer and within the insulating layer opening and the masking layer opening, wherein;

the semiconductor layer includes a top doped portion, a bottom doped portion, and a wall portion;

the top doped portion has a first conductivity type and lies near the top of the insulating layer opening;

the bottom doped portion has the first conductivity type and lies lie along the bottom of the insulating layer opening;

the wall portion has a second conductivity type that is opposite the first conductivity type and lies along the wall of the insulating layer opening and between the top doped and bottom doped portions of the semiconductor layer; and

part of the top doped portion overlies the insulating layer opening and the bottom doped portion but does not overlie the wall portion;

a gate dielectric layer lying adjacent to the semiconductor layer and including a portion of the semiconductor layer that lies within the insulating layer opening; and

a gate electrode that lies adjacent to the gate dielectric layer.

10. The semiconductor device of claim 9, wherein:

the substrate has a primary surface;

the masking layer has an edge adjacent to the masking layer opening;

the masking layer opening includes a center such that a line through the center in a direction generally normal to the primary surface forms a lateral centerline;

a first point is located where the wall and the bottom of the insulating layer opening meet;

a second point is that point located on the edge of the masking layer adjacent to the masking layer opening that is closest to the first point; and

the first point and second point form a line having an angle at least about 0.5 degrees as measured from the lateral centerline.

13. The semiconductor device of claim 9, wherein the masking layer and the semiconductor layer both include silicon.

14. The semiconductor device of claim 9, further comprising a conductive barrier layer underlying the bottom doped portion.

15. The semiconductor device of claim 9, wherein the vertical thin-film field-effect transistor is a load transistor of a static-random-access memory cell.