Receiver circuit for digital and analog modulated signal

• US 5,416,802 A
• Filed: 05/20/1993
• Issued: 05/16/1995
• Est. Priority Date: 05/20/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ishii, Junichi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Vo, Don N.
• Application Number:
  US08/063,694
• Time in Patent Office: 726 Days
• Field of Search: 375/5, 375/75, 455/33.1, 455/212, 455/218, 455/221, 379/58, 379/59, 381/120
• US Class Current: 375/316
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04M 1/72502 with one base station connected to a single line

Abstract

A receiver circuit for receiving both digital and analog modulated signals has a high frequency amplifier for amplifying digital and analog modulated high frequency signals, a down conversion block for converting an output signal from the high frequency amplifier into an intermediate frequency signal, a root Nyquist bandpass filter for limiting the intermediate frequency signal from the down conversion block to a frequency band based on root Nyquist characteristics, an intermediate frequency signal linear amplifier for linearly amplifying the intermediate frequency signal from the root Nyquist bandpass filter, a limiter amplifier for limiting to a constant amplitude the intermediate frequency signal from the intermediate frequency signal linear amplifier, a received signal intensity detector for detecting received signal intensity information from the intermediate frequency signal from the intermediate frequency signal linear amplifier, a synchronizing clock signal generator for generating a synchronizing clock signal from the received signal intensity information from the received signal intensity detector, a digital demodulator for demodulating a digital modulated intermediate frequency signal from the limiter amplifier based on the synchronizing clock signal, and an analog demodulator for demodulating an analog modulated intermediate frequency signal from the limiter amplifier.

Claims

1. A receiver circuit for receiving both digital and analog modulated signals, comprising:

a frequency converter for converting digital and analog modulated high frequency signals into respective intermediate frequency signals;

a root Nyquist bandpass filter for limiting the intermediate frequency signal from said frequency converter to a frequency band based on root Nyquist characteristics;

an intermediate frequency signal linear amplifier for linearly amplifying the intermediate frequency signal that has passed through said root Nyquist bandpass filter;

a limiter amplifier for limiting to a constant amplitude the intermediate frequency signal from said intermediate frequency signal linear amplifier;

a digital demodulator connected to said limiter amplifier for demodulating the digital modulated intermediate frequency signal from said limiter amplifier; and

an analog demodulator connected to said limiter amplifier parallel to said digital demodulator for demodulating the analog modulated intermediate frequency signal from said limiter amplifier.

2. A receiver circuit according to claim 1 that further comprises a received signal intensity detector for detecting received signal intensity information from the intermediate frequency signal amplified by said intermediate frequency signal linear amplifier.

3. A receiver circuit according to claim 2 that further comprises a first synchronizing clock signal generator for generating a synchronizing clock signal from the received signal intensity information detected by said received signal intensity detector and applying said synchronizing clock signal to said digital demodulator.

4. A receiver circuit according to claim 1 or 2 that further comprises a second synchronizing clock signal generator for generating a synchronizing clock signal from the digital modulated intermediate frequency signal from said limiter amplifier and applying said synchronizing clock signal to said digital demodulator.

5. A receiver circuit according to claim 1 that further comprises a high frequency amplifier for amplifying the digital and analog modulated high frequency signals and applying the amplified high frequency signals to said frequency converter.

6. A receiver circuit according to claim 5 that further comprises a bandpass filter connected between said high frequency amplifier and said frequency converter for limiting an output signal from said high frequency amplifier to a predetermined frequency band.