Process for digital transmission and direct conversion receiver

• US 5,416,803 A
• Filed: 05/20/1993
• Issued: 05/16/1995
• Est. Priority Date: 09/26/1991
• Status: Expired due to Fees

• Current Assignee: Societe Anonyme DBA
• Original Assignee: Alcatel Telspace
• Inventors: Janer, Patrick
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Vo, Don N.
• Application Number:
  US08/064,074
• Time in Patent Office: 726 Days
• Field of Search: 375/80, 375/94, 375/97, 375/120, 375/81, 455/214, 331/25, 331/1 R, 331/1 A, 329/325, 329/336, 332/127, 332/128, 332/129
• US Class Current: 375/324
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0053 Closed loops
• CPC Class Codes: H04L 27/2071 in which the data are represented by the carrier phase, e.g. systems with differential coding
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

The transmitter uses a synthesized oscillator (1A) whose reference (24) is provided by the clock (H) of the data (P, Q). The demodulation oscillator (13A) of the receiver is a synthesizer which is functionally identical to that (1A) of the transmitter, and its reference (23) is provided by the clock (H, 36) recovered from the received data.

Claims

1. A digital data transmission system for transmitting data, in particular, by a microwave radio beam, said system comprising:

at least one transmitter for transmitting digital data on a microwave carrier, said transmitter comprising

a first frequency synthesizer for generating the microwave carrier frequency, a reference frequency for the first frequency synthesizer being provided by the clock frequency of the digital data to be transmitted; and

at least one receiver for receiving said digital data transmitted by said at least one transmitter as a received digital data signal, said receiver comprising;

a demodulator for performing coherent demodulation on said received digital data signal directly at microwave frequency and outputting a demodulated received digital data signal;

a baseband processor for processing in baseband said demodulated received digital data signal and outputting a baseband processed demodulated received digital data signal;

a clock recovery circuit for recovering the clock frequency from the baseband processed demodulated received digital data signal;

another frequency synthesizer operating as a demodulation oscillator to provide an output signal, said another frequency synthesizer being at least functionally identical to the first frequency synthesizer and having its reference frequency provided in similar manner by the clock frequency recovered from the baseband processed demodulated received digital data signal, a frequency of said output signal of said demodulation oscillator being identical to said microwave carrier frequency and being synchronous therewith; and

an auxiliary phase offset circuit for receiving the output signal from said demodulation oscillator, and adjusting said output signal to compensate for any phase offsets generated by said clock recovery circuit and to output a control input signal in accordance therewith to the demodulator, said demodulator performing said coherent demodulation in accordance with said control input signal.

2. A digital transmission system as claimed in claim 1, further comprising a phase estimator which receives said baseband processed demodulated received digital data signal and provides an output signal in accordance therewith to control said auxiliary phase offset circuit.

3. A digital transmission system according to claim 1, wherein said first frequency synthesizer comprises a divider for dividing the clock frequency H by a variable number N1, and an adjustable divider for dividing, by a number N2, a portion of the microwave carrier frequency being fed back to be combined with said clock frequency H divided by said divider, so that the microwave carrier frequency F output by the first frequency synthesizer is equal to:

space="preserve" listing-type="equation">F=H×

N2/N1