Semiconductor integrated circuit with functional blocks capable of being individually tested externally
First Claim
1. A semiconductor integrated circuit formed on a single semiconductor chip and including an address bus, a data bus and a control bus, said semiconductor integrated circuit comprising:
- a central processing unit for performing arithmetic processings;
peripheral circuits associated with said central processing unit;
external terminals connected to said address bus, said data bus and said control bus communicating with external devices;
a test mode setting circuit connected to said external terminals for receiving test signals inputted through said external terminals, and generating control signals in response to said inputted test signals; and
a signal control circuit connected to said address bus, said data bus and said control bus,said signal control circuit having means for connecting one of said central processing unit and said peripheral circuits to said address bus, said data bus and said control bus in response to said control signals received from said test mode setting circuit for selecting said one of said central processing unit and said peripheral circuits to receive digital signals from said address bus, said data bus and said control bus and to output digital signals to said data bus so that said selected one of said central processing unit and said peripheral circuits operates with said buses.
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Accused Products
Abstract
A semiconductor integrated circuit which includes a central processing unit, one or more peripheral circuits, one or more external terminals for transferring signals to or from the integrated circuit, and circuits for selecting the central processing unit or one of the peripheral circuits and solely operating the selected one in a test mode. The circuit for selecting includes a test mode control circuit and a signal control circuit. The test mode control circuit generates and supplies control signals in response to test operating signals having particular timings different from those of an actual operating signal inputted through the external terminal in a normal mode. The signal control circuit serves to separate the selected one from the others in a manner to allow the separated one to solely operate in the test mode.
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Citations
5 Claims
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1. A semiconductor integrated circuit formed on a single semiconductor chip and including an address bus, a data bus and a control bus, said semiconductor integrated circuit comprising:
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a central processing unit for performing arithmetic processings; peripheral circuits associated with said central processing unit; external terminals connected to said address bus, said data bus and said control bus communicating with external devices; a test mode setting circuit connected to said external terminals for receiving test signals inputted through said external terminals, and generating control signals in response to said inputted test signals; and a signal control circuit connected to said address bus, said data bus and said control bus, said signal control circuit having means for connecting one of said central processing unit and said peripheral circuits to said address bus, said data bus and said control bus in response to said control signals received from said test mode setting circuit for selecting said one of said central processing unit and said peripheral circuits to receive digital signals from said address bus, said data bus and said control bus and to output digital signals to said data bus so that said selected one of said central processing unit and said peripheral circuits operates with said buses. - View Dependent Claims (2, 3, 4, 5)
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Specification