Semiconductor integrated circuit with functional blocks capable of being individually tested externally

• US 5,416,919 A
• Filed: 12/21/1992
• Issued: 05/16/1995
• Est. Priority Date: 07/19/1989
• Status: Expired due to Term

• Current Assignee: Sharp Electronics Corporation (Hon Hai Precision Industry Co., Ltd.), Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ogino, Eiji, Wada, Masahiko, Imai, Shigeki, Yoshii, Takeshi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): HUA, LY
• Application Number:
  US07/996,853
• Time in Patent Office: 876 Days
• Field of Search: 371/15.1, 371/16.1, 371/22.1, 371/22.6, 364/580, 364/579, 324/158 R, 324/73.1, 395/575
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's

Abstract

A semiconductor integrated circuit which includes a central processing unit, one or more peripheral circuits, one or more external terminals for transferring signals to or from the integrated circuit, and circuits for selecting the central processing unit or one of the peripheral circuits and solely operating the selected one in a test mode. The circuit for selecting includes a test mode control circuit and a signal control circuit. The test mode control circuit generates and supplies control signals in response to test operating signals having particular timings different from those of an actual operating signal inputted through the external terminal in a normal mode. The signal control circuit serves to separate the selected one from the others in a manner to allow the separated one to solely operate in the test mode.

Claims

1. A semiconductor integrated circuit formed on a single semiconductor chip and including an address bus, a data bus and a control bus, said semiconductor integrated circuit comprising:

a central processing unit for performing arithmetic processings;

peripheral circuits associated with said central processing unit;

external terminals connected to said address bus, said data bus and said control bus communicating with external devices;

a test mode setting circuit connected to said external terminals for receiving test signals inputted through said external terminals, and generating control signals in response to said inputted test signals; and

a signal control circuit connected to said address bus, said data bus and said control bus,

said signal control circuit having means for connecting one of said central processing unit and said peripheral circuits to said address bus, said data bus and said control bus in response to said control signals received from said test mode setting circuit for selecting said one of said central processing unit and said peripheral circuits to receive digital signals from said address bus, said data bus and said control bus and to output digital signals to said data bus so that said selected one of said central processing unit and said peripheral circuits operates with said buses.

2. A semiconductor integrated circuit according to claim 1, wherein said test mode setting circuit receives said test signals through said data bus and said control signal bus, and supplies said control signals to said signal control circuit through an internal bus connected between said test mode setting circuit and said signal control circuit.

3. A semiconductor integrated circuit according to claim 1, wherein said central processing unit is responsive to said test signals for producing a bus acknowledgement signal and a selected one of said peripheral circuits is connected to said address bus, said data bus and said control bus when said bus acknowledgement signal is outputted from said central processing unit.

4. A semiconductor integrated circuit according to claim 1, in which said test mode setting circuit generates a signal for preventing the operation of said semiconductor integrated circuit from being changed from a normal mode to a test mode when said test signals are irregular.

5. A semiconductor integrated circuit according to claim 1, wherein said external terminals, said address bus, said data bus, and said control bus are used in both a normal mode and a test mode.