Single event upset immune logic family

• US 5,418,473 A
• Filed: 10/28/1992
• Issued: 05/23/1995
• Est. Priority Date: 10/28/1992
• Status: Expired due to Term

• Current Assignee: Idaho Research Foundation, Inc.
• Original Assignee: Idaho Research Foundation, Inc.
• Inventors: Canaris, John
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/967,457
• Time in Patent Office: 937 Days
• Field of Search: 307/44 B, 307/451, 307/296.5, 307/272.2, 307/279
• US Class Current: 326/27
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A complete logic family which is SEU immune is constructed, using logic/circuit design techniques, to recover from an SEU, regardless of the shape of the upsetting event. The logic family provides a redundancy of data to be used to restore data lost by an SEU. Two transistor networks are used, a p-channel network and an n-channel network. Each transistor network consists of a plurality of input transistors and a feedback transistor. The feedback transistor is sized to be weak compared to the input transistors. The transistor networks are designed to either resist an SEU or to shutdown until the SEU is over and then the network which is not shutdown will restore the data of the network that was hit by the SEU. The logic family can prevent glitch propagation from an upset node and can be implemented in a standard, commercial CMOS process without any additional processing steps. The logic family includes but is not limited to an Inverter, 2-input Nand, 2-input Nor, 3-input OrNand and a 3-input AndNor. The SEU recovery mechanism used by the logic family can be extended to logic structures in general. The SEU recovery mechanism is independent of the duration or shape of the upsetting event.

Claims

1. A single event upset immune logic circuit having a plurality of inputs, a first output and a second output, comprising:

a. means for suppressing transient aspects of a single event upset; and

b. means for coupling both the first output and the second output together using a first feedback path and a second feedback path for maintaining a source of uncorrupted data for use in restoring data that is lost in a single event upset

wherein the logic circuit comprises 2n+2 transistors, where n is equal to the number of inputs to the circuit.

2. The apparatus as claimed in claim 1 wherein the single event upset immune logic circuit is implemented using a CMOS process.

3. The apparatus as claimed in claim 2 wherein the transistors are all enhancement mode MOSFET transistors.

4. A single event upset immune logic circuit comprising:

a. a first transistor network comprising a first plurality of transistors;

b. a second transistor network coupled to the first transistor network, comprising a second plurality of transistors;

c. a first plurality of inputs coupled to the first transistor network for driving only the first transistor network, the first network having a first output for providing a first logic state which cannot be upset;

d. a second plurality of inputs coupled to the second transistor network for driving only the second transistor network, the second network having a second output for providing a second logic state which cannot be upset;

e. means for restoring a first logic state destroyed in the second network by a single event upset comprising a first feedback path for coupling the first output to control the second network; and

f. means for restoring a second logic state destroyed in the first network by a single event upset comprising a feedback path for coupling the second output to the first network.

5. The apparatus as claimed in claim 4 wherein a first load transistor in the first network is sized to be weak compared to one or more first logic transistors in the first network and a second load transistor in the second network is sized to be weak compared to one or more second logic transistors in the second network.

6. The apparatus as claimed in claim 4 wherein the logic circuit comprises 2n+2 transistors, where n is equal to the number of inputs in the circuit.

7. The apparatus as claimed in claim 4 wherein the single event upset immune logic circuit is implemented using a CMOS process.

8. A single event upset immune inverter having a first input, a second input, a first output and a second output, comprising:

a. a first transistor coupled to the first input for providing a source of a first logic state which cannot be upset;

b. a second transistor coupled to the second input for providing a source of a second logic state which cannot be upset;

c. a first output coupled to the first transistor;

d. a second output having the same logic state value as the first output, unless either the first output or the second output have been hit by a single event upset, coupled to the second transistor; and

e. means for coupling the first output to the second output to restore either the first output or the second output to the same logic state value as the first output or the second output if either the first output or the second output have been hit by a single event upset.

9. The apparatus as claimed in claim 8 wherein the first plurality of transistors comprises a first transistor and a second transistor, the second transistor sized to be weak compared to the first transistor and the second plurality of transistors comprises a third transistor and a fourth transistor, the fourth transistor sized to be weak compared to the third transistor.

10. The apparatus as claimed in claim 8 wherein the single event upset immune inverter is implemented using a CMOS process.

11. The apparatus as claimed in claim 8 wherein the means for coupling the first output to the second output is comprised of a first feedback path coupled to the first transistor and a second feedback path coupled to the second transistor.

12. The apparatus as claimed in claim 8 wherein the transistors of both the first plurality and the second plurality are enhancement mode MOSFET transistors.

13. A single event upset immune CMOS inverter having a first input and a second input and a first output and a second output, coupled to a power supply and ground comprising:

a. a first p-channel transistor having a first gate, a first source and a first drain, the first gate coupled to the first input, the first drain coupled to the power supply and the first source coupled to the first output;

b. a second p-channel transistor having a second gate, a second source and a second drain, the second gate coupled to the second output, the second source coupled to the ground and the second drain coupled to the first drain and the first output;

c. a third n-channel transistor having a third gate, a third source and a third drain, the third gate coupled to the first source, the second drain and the first output, the third drain coupled to the power supply and the third source coupled to the second gate and the second output; and

d. a fourth n-channel transistor having a fourth gate, a fourth source and a fourth drain, the fourth gate coupled to the second input, the fourth source coupled to the ground and the fourth drain coupled to the second gate, the third source and the second output.

14. A single event upset immune CMOS two-input NAND gate having a first input, a second input, a third input and a fourth input and a first output and a second output, coupled to a power supply and ground, comprising:

a. a first p-channel transistor having a first gate, a first source and a first drain, the first gate coupled to the first input, the first drain coupled to the power supply and the first source coupled to the first output;

b. a second p-channel transistor having a second gate, a second source and a second drain, the second gate coupled to the second input, the second drain coupled to the power supply and the second source coupled to the first source and to the first output;

c. a third p-channel transistor having a third gate, a third source and a third drain, the third gate coupled to the second output, the third source coupled to the ground and the third drain coupled to the first source, the second source and the first output;

d. a fourth n-channel transistor having a fourth gate, a fourth source and a fourth drain, the fourth gate coupled to the third input and the fourth drain coupled to the third gate and the second output;

e. a fifth n-channel transistor having a fifth gate, a fifth source and a fifth drain, the fifth gate coupled to the fourth input, the fifth source coupled to the ground and the fifth drain coupled to the fourth source; and

f. a sixth n-channel transistor having a sixth gate, a sixth source and a sixth drain, the sixth gate coupled to the first and second sources and to the third drain and the first output, the sixth drain coupled to the power supply and the sixth source coupled to the third gate, the fourth drain and the second output.