Fuse state sense circuit

• US 5,418,487 A
• Filed: 09/04/1992
• Issued: 05/23/1995
• Est. Priority Date: 09/04/1992
• Status: Expired due to Term

• Current Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Original Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Inventors: Armstrong, Gene L. II
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US07/940,612
• Time in Patent Office: 991 Days
• Field of Search: 307/202.1, 307/465, 307/468, 365/96, 365/225.7
• US Class Current: 327/525
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A fuse state sense circuit includes a fusible link (40) that is disposed between a node (38) and ground. A programming/sense pad (42) is provided to allow voltage to be applied to the node (38) external to the fuse state sense circuit. Current is provided to the node (38) through a current source (30) and a transistor (36). The transistor (36) is controlled by a bias current. An output node (32) is disposed between the current source (30) and the transistor (36). This is connected to the output through an inverter (34). In operation, the voltage on node (38) is raised to a first level to turn off transistor (36) to allow the output to be exercised and to change the state thereof to emulate the fusible link (40) being open. In a second and programming mode, the voltage on the node (38) is raised to a much higher level to allow sufficient current to flow through fusible link (40) to open it. Transistor ( 36) in this mode is rendered non-conductive and isolates the node (38) from the remaining portion of the circuit.

Claims

1. A method for programming and sensing the state of a fusible link having a first intact state and a second open state, comprising the steps of:

providing a fuse node, the fusible link connected between the fuse node and a low reference voltage level;

providing an output node having first and second logic states;

driving current through the output node and the fusible link from a high reference voltage level when the fusible link is in the first intact state, the step of driving pulling the output node to the low reference voltage level corresponding to the first logic state on the output node;

sensing the state of the fusible link by the step of applying a sense voltage from an external source to the fuse node, the sense voltage having a level above a predetermined threshold level but below a level that will cause damage to the fusible link, the step of applying the sense voltage substantially interrupting current through the output node such that the step of driving drives the output node to the high reference voltage level corresponding to the second logic state on the output node;

monitoring the output node to determine the state of the fusible link; and

removing the sense voltage from the fuse node without damaging the fuse after the step of monitoring.

2. The method of claim 1, wherein the step of driving comprises the steps of:

connecting a current source between the high reference voltage and the fuse node through the output node; and

conducting a substantially constant current through the current source to the fuse node through the output node when the fusible link is in the first intact state such that the output node is pulled to the low reference voltage level.

3. The method of claim 1, wherein the step of sensing comprises providing a sense transistor having a source/drain path and a gate and disposing the source/drain path of the sense transistor between the fuse node and the output node and biasing the gate to a voltage level sufficient to allow the sense transistor to conduct when the fusible link is in the first intact state and the step of applying the sense voltage to the fuse node substantially rendering the sense transistor substantially non-conductive.

4. The method of claim 1, and further comprising, programming the fusible link to the second open state from the first intact state by applying a programming voltage to the fuse node, the programming voltage being substantially above the predetermined sense threshold level voltage, wherein current is substantially interrupted to the fuse node and to the output node such that the output node is driven to the high reference voltage level corresponding to the second logic state on the output node.

5. The method of claim 4, wherein the step of programming further includes isolating the fuse node from the output node when the programming voltage is applied to the fuse node such that current is prevented from flowing from the fuse node to the output node and to the high reference voltage level.