Retry scheme for controlling transactions between two busses

• US 5,418,914 A
• Filed: 10/25/1993
• Issued: 05/23/1995
• Est. Priority Date: 09/17/1991
• Status: Expired due to Term

• Current Assignee: NCR Corporation (NCR Voyix Corporation)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Miller, Marti D., Walrath, Craig A., Heil, Thomas F., McDonald, Edward A., Ottinger, James M., Young, Gene F.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/143,393
• Time in Patent Office: 575 Days
• Field of Search: 395/325, 395/725, 395/275, 395/425
• US Class Current: 710/113
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.

Claims

1. In a computer system including a plurality of bus masters connected a common bus, a shared resource connected to said common bus, said shared resource having available and unavailable states, and a bus arbiter for controlling bus master access to said common bus, a method for optimizing use of said common bus, comprising the steps of:

sensing the state of said shared resource;

generating a retry signal when a first one of said plurality of bus masters gaining control of said common bus addresses said shared resource while said shared resource is in an unavailable state;

providing said retry signal to said first bus master, said first bus master relinquishing control of said common bus upon receipt of said retry signal;

identifying said first bus master to said arbiter; and

generating a busy signal as long as said shared resource is unavailable and providing said busy signal to said bus arbiter, said arbiter preventing said first bus master from arbitrating for control of said common bus during receipt of said busy signal.

2. The method according to claim 1, further including the step of:

granting said first bus master control of said bus upon the expiration of said busy signal.

3. In a computer system including a plurality of bus masters connected to a first bus, a bus arbiter for controlling bus master access to said first bus, and an interface circuit providing coupling between said first bus and a second bus, apparatus comprising:

logic within said interface circuit for generating a busy signal whenever said second bus is in a busy state, said busy signal being provided to said bus arbiter; and

logic within said arbiter for preventing bus masters that are seeking control of said first bus to access said interface unit and said second bus from participating in arbitration for control of said first bus during receipt of said busy signal.

4. In a computer system including a first bus, a second bus, and a plurality of bus masters coupled to said first bus, apparatus comprising:

an interface circuit connecting said first and second busses, said interface circuit including;

logic for generating a busy signal when said second bus is in a busy state;

logic for generating a retry signal when said interface circuit is addressed by one of said plurality of bus masters seeking access to said second bus while said second bus is in a busy state, said retry signal being simultaneously provided to each one of said plurality of bus masters;

logic within each one of said plurality of bus masters for receiving said retry signal and relinquishing control of said first bus in response thereto; and

an arbiter for controlling use of said first bus, said arbiter including;

logic for receiving said busy signal and preventing said bus master seeking access to said second bus from participating in arbitration for control of said first bus during receipt of said busy signal;

whereby bus masters not seeking access to said second bus are not blocked from arbitrating for control of said first bus during receipt of said busy signal by said arbiter.