Register allocation by decomposing, re-connecting and coloring hierarchical program regions

• US 5,418,958 A
• Filed: 07/15/1992
• Issued: 05/23/1995
• Est. Priority Date: 07/15/1992
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Goebel, Kurt J.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): BACKENSTOSE, JONATHAN
• Application Number:
  US07/914,860
• Time in Patent Office: 1,042 Days
• Field of Search: 395/700, 364/247, 364/247.4, 364/260, 364/260.2, 364/280, 364/280.4, 364/280.5
• US Class Current: 717/156
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space

Abstract

During code generation, a routine is first decomposed into regions. Then, starting from the highest plateau, i.e. the inner most control flow level, the interference graph of each region in a plateau is colored individually. Neighboring regions of the plateau are then combined by connecting the colored nodes of the interference graphs that are live at region boundaries. If connecting the interference graphs render the connected interference graph uncolorable, colored nodes that are live at region boundaries are connected by introducing register to register move or spilling the node. When all neighboring regions of a plateau are combined, the plateau collapses into a region of the lower level plateau. The process is repeated until all plateaus are collapsed and the regions of the base plateau are colored and combined together. Registers are then allocated to the colored nodes.

Claims

1. In a computer system comprising a CPU and a plurality of registers coupled to said CPU for executing a high Level language compiler and program routines compiled by said compiler, a method for said compiler to allocate registers for a program routine during code generation while compiling said program routine, said method comprising the steps of:

a) decomposing said program routine into regions, said regions comprising non-overlapping basic blocks of said program routine, said regions having three distinct types, a Subsume type, a Join type and a Merge type, said Subsume type regions being regions comprising inner and outer loops of said program routine, said Join type regions being regions comprising parts of conditional statements of said program routine, said Merge type regions being regions comprising a selected one of (i) parts of a basic block, and (ii) independent loops, of said program routine;

b) constructing interference graphs of said regions individually, said interference graphs comprising nodes representing variables and edges connecting said nodes representing conflicts between said nodes, two nodes are connected by an edge if the two variables represented by nodes cannot simultaneously share a register at some point in the program routine;

c) coloring the interference graphs of said regions

d) connecting said colored interference graphs of said regions, each pair of said interference graphs being connected at colored nodes that are live over region boundaries of said regions; and

e) repeating steps (c) and (d) until a composite interference graph representing the entire routine is connected and colored

f) allocating registers to colored nodes of said composite interference graph.

2. The method as set forth in claim 1, wherein, said program routine is decomposed into regions in said step a) using a hierarchical reduction algorithm.

3. The method as set forth in claim 1, wherein,

said program routine comprises a plurality of nested control flow levels;

said steps b) and c) being repeated for each of said nested control flow level starting with the inner most control flow level to the outer most control flow level, each of said control flow level, except the outer most control flow level, collapsing into a region of the next outer control flow level when its regions'"'"' colored interference graphs are connected in said step c).

4. The method as set forth in claim 3, wherein, if connecting said interference graphs at said live colored nodes renders said connected interference graph uncolorable, said interference, graphs are connected as follows:

if a live colored node is referenced in both regions, said interference graphs are connected by adding a register to register move to avoid a register spill at said live colored node; and

if a live colored node is not referenced in both regions, said interference graphs of said regions are connected by adding a register spill into memory at said colored node.

5. The method as set forth in claim 3, wherein,

said computer system comprises a plurality of parallel processors;

said regions comprise regions of at least two types, a Join type and a Merge type, said Join type regions being regions comprising parts of conditional statements of said program routine, said Merge type regions being regions comprising a selected one of (i) parts of a basic block, and (ii) independent loops, of said program routine; and

said interference graphs of said regions having a region type of a selected one of said Merge and said Join type are colored individually in parallel, regardless which control flow levels said Merge and Join regions are located.

6. In a computer system comprising a central processing unit (CPU) and a plurality of registers coupled to said CPU for executing a high level language compiler and program routines compiled by said compiler, a code generator of said compiler for allocating registers for a program routine during code generation while compiling said program routine, said code generator comprising:

a) decomposing means for decomposing said program routine into regions, said regions comprising non-overlapping basic blocks of said program routine, said regions having three distinct types, a Subsume type, a Join type and a Merge type, said Subsume type regions being regions comprising inner and outer loops of said program routine, said Join type regions being regions comprising parts of conditional statements of said program routine, said Merge type regions being regions comprising a selected one of (i) parts of a basic block, and (ii) independent loops, of said program routine;

b) coloring means coupled to said decomposing means for constructing and coloring interference graphs of said regions individually, said interference graphs comprising nodes representing variables, and edges connecting said nodes representing conflicts between said registers, wherein two nodes are connected by an edge if the two variables represented by nodes cannot simultaneously share a register during execution of the program routine;

c) connecting means coupled to said coloring means for connecting said colored interference graphs of said regions, each pair of said interference graphs being connected at colored nodes that are live over region boundaries of said regions; and

d) allocating means coupled to said connecting means for allocating registers to colored nodes of said connected interference graphs.

7. The code generator as set forth in claim 6, wherein, said decomposing means decomposes said program routine into regions using an hierarchical reduction algorithm.

8. The code generator as set forth in claim 6, wherein,

said program routine comprises a plurality of nested control flow levels;

said coloring and connecting means repeats said coloring and said connecting for each of said nested control flow level starting with the inner most control flow level to the outer most control flow level, each of said control flow level, except the outer most control flow level, collapsing into a region of the next outer control flow level when its regions'"'"' colored interference graphs are connected.

9. The code generator as set forth in claim 8, wherein, if connecting said interference graphs at said live colored nodes render said connected interference graph uncolorable, said coloring and connecting means connects and colors said interference graphs as follows:

if a live colored node is referenced in both regions, said connecting means connects said interference graphs by adding a register to register move to avoid a register spill at said live colored node; and

if a live colored node is not referenced in both regions, said connecting means connects said interference graphs by adding a register spill into memory at said live colored node.

10. The code generator as set forth in claim 8, wherein,

said computer system comprises a plurality of parallel processors;

said regions comprise regions of at least two types, a Join type and a Merge type, said Join type regions being regions comprising parts of conditional statements of said program routine, said Merge type regions being regions comprising a selected one of (i) parts of a basic block, and (ii) independent loops, of said program routine; and

said coloring means colors said interference graphs of said regions having a region type of a selected one of said Merge and said Join type in parallel, regardless which control flow levels said Merge and Join regions are located.