×

Digital computer system with cache controller coordinating both vector and scalar operations

  • US 5,418,973 A
  • Filed: 06/22/1992
  • Issued: 05/23/1995
  • Est. Priority Date: 06/22/1992
  • Status: Expired due to Term
First Claim
Patent Images

1. A digital computer system comprising, in combination:

  • a scalar central processing unit;

    a vector processor; and

    a cache memory coupled to said scalar central processing unit for scalar reads and writes between said scalar central processing unit and said cache memory, and coupled to said vector processor for vector loads and stores between said vector processor and said cache memory;

    wherein said scalar processing unit includes;

    (a) an execution unit for executing scalar instructions and for issuing vector instructions to said vector processor,(b) a memory management unit for translating virtual addresses of both said scalar instructions and said vector instructions to physical addresses, and(c) a cache controller unit for coordinating data transfer between said scalar central processing unit and said cache memory; and

    wherein said execution unit includes means for computing virtual memory addresses of vector elements specified by vector load and vector store instructions and sending the virtual memory addresses to said memory management unit for translation to physical addresses,wherein said cache controller unit includes means for coordinating both;

    (a) vector loads and stores between said vector processor and said cache memory, and(b) scalar reads and writes between said scalar central processing unit and said cache memory; and

    wherein said cache controller unit, said cache memory, and said vector processor are directly connected together by a common address bus and a common data bus;

    wherein said cache controller unit includes a write queue for queuing both;

    (a) scalar physical write addresses and scalar write data, and(b) physical addresses of said vector elements of said vector store instructions; and

    means for servicing said write queue by addressing said cache memory with said scalar physical write addresses in said write queue for scalar operations and by addressing said cache memory for vector operations with said physical addresses of said vector elements in said write queue.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×