Wide instruction word architecture central processor
First Claim
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1. A central processor of the type used for scientific-technical, economic-statistical computations, and for solving the problems of automation of designing, modelling and controlling operations with the architecture of a wide instruction word, assuring high efficiency on both vector and scalar calculations, comprising and interface unit (10) coupling the central processor with common main internal memory via an exchange bus (30);
- a multichannel arithmetical logical unit (5) for performing operations in speculative and normal modes of operation;
a data switch (4) connecting the input of arithmetical logical unit (5) with an output of said arithmetical logical unit and with a data buffer memory (3) comprising a data stack of procedures and a subset of array elements preloaded for a preliminary treatment in a loop;
a data cache memory (8) coupled to said interface unit (10) for storing global data absent in the data buffer memory (3);
a load store unit (6) coupled to said data switch and said data cache memory for calculating scalar addresses; and
a multichannel indexing unit (7) coupled to said load store unit for calculating vector addresses for data exchange with the common main internal memory via a translation lookaside buffer (9) executing a load of a current line of the corresponding virtual to physical address and additionally, for vectors, a preliminary load of a line of a next virtual page;
a subprogram unit (11) for the preparation of an address environment, the prefetch of a new program code and control of procedure transfer without breaking of the instruction decoding coupled to the data cache memory (8), said unit (9) and with a control unit (2) for providing parallel start of said multichannel arithmetical logical unit (5), the load store unit (6) and the multichannel indexing unit(7), and for the preliminary concurrent preparation of transfers of control, and also connected to the data buffer memory (3), an instruction buffer memory (1) coupled to a control unit (12) which stores a working code set of procedures and coupled to the control unit 2;
a control attributes unit (13) for the transfer of control along one of the prepared transfers of control without breaking the clocks with the dynamic renaming of control attributes addresses in a loop; and
an operand readiness unit (14) for operands pre-requested from the common main internal memory;
said control attributes unit (13) being coupled with the arithmetical logical unit (5) and the control unit (2), and the said unit (14) being connected to said control unit (2), the interface unit (10) and the translation lookaside buffer (9).
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Abstract
A central processor for scientific-technica, economic-statistical computations, for solving the problems of modelling and control with the architecture of an extended instruction work comprises instruction data buffer memories 1 and 3, respectively, a control device 2, a data commutator 4, an arithmeticologic device 5, record-calling, indexing, associative memory, mathematical-to-physical address conversion, interface, subprogram device (6-11), as well as a control character device 13 and an operand readiness device 14, and provides high efficiency both on vector and scalar computations.
20 Citations
1 Claim
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1. A central processor of the type used for scientific-technical, economic-statistical computations, and for solving the problems of automation of designing, modelling and controlling operations with the architecture of a wide instruction word, assuring high efficiency on both vector and scalar calculations, comprising and interface unit (10) coupling the central processor with common main internal memory via an exchange bus (30);
- a multichannel arithmetical logical unit (5) for performing operations in speculative and normal modes of operation;
a data switch (4) connecting the input of arithmetical logical unit (5) with an output of said arithmetical logical unit and with a data buffer memory (3) comprising a data stack of procedures and a subset of array elements preloaded for a preliminary treatment in a loop;
a data cache memory (8) coupled to said interface unit (10) for storing global data absent in the data buffer memory (3);
a load store unit (6) coupled to said data switch and said data cache memory for calculating scalar addresses; and
a multichannel indexing unit (7) coupled to said load store unit for calculating vector addresses for data exchange with the common main internal memory via a translation lookaside buffer (9) executing a load of a current line of the corresponding virtual to physical address and additionally, for vectors, a preliminary load of a line of a next virtual page;
a subprogram unit (11) for the preparation of an address environment, the prefetch of a new program code and control of procedure transfer without breaking of the instruction decoding coupled to the data cache memory (8), said unit (9) and with a control unit (2) for providing parallel start of said multichannel arithmetical logical unit (5), the load store unit (6) and the multichannel indexing unit(7), and for the preliminary concurrent preparation of transfers of control, and also connected to the data buffer memory (3), an instruction buffer memory (1) coupled to a control unit (12) which stores a working code set of procedures and coupled to the control unit 2;
a control attributes unit (13) for the transfer of control along one of the prepared transfers of control without breaking the clocks with the dynamic renaming of control attributes addresses in a loop; and
an operand readiness unit (14) for operands pre-requested from the common main internal memory;
said control attributes unit (13) being coupled with the arithmetical logical unit (5) and the control unit (2), and the said unit (14) being connected to said control unit (2), the interface unit (10) and the translation lookaside buffer (9).
- a multichannel arithmetical logical unit (5) for performing operations in speculative and normal modes of operation;
Specification
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Current AssigneeInstitut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni SA Lebedeva Akademii NAUK SSSR
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Original AssigneeInstitut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni SA Lebedeva Akademii NAUK SSSR
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InventorsSakhin, July K., Kim, Alexandr K., Semenikhin, Sergei V., Volkonsky, Vladimir J., Nazarov, Leonid N., Babaian, Boris A., Gorshtein, Valery Y.
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Primary Examiner(s)McElheny, Jr., Donald E.
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Application NumberUS07/971,910Time in Patent Office886 DaysField of Search364/401, 364/232.21, 364/228.7, 364/228.8, 364/228.9, 364/231.9, 364/232.21, 364/232.9, 364/931.41, 364/931.42, 364/931.51, 364/931.52 , 364/937.7, 395/800US Class Current712/24CPC Class CodesG06F 15/8053 Vector processorsG06F 9/3885 using a plurality of indepe...
