Simplified contact method for high density CMOS

• US 5,420,057 A
• Filed: 06/30/1994
• Issued: 05/30/1995
• Est. Priority Date: 06/30/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bennett, Reid S., Yee, Dennis S.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/269,856
• Time in Patent Office: 334 Days
• Field of Search: 437/40, 437/41, 437/44, 437/913, 437/984, 148/DIG. 141
• US Class Current: 438/233
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: Y10S 148/141 Self-alignment coat gate

Abstract

A self-aligned method of forming contacts to a transistor gate, source and drain reduces the required spacing between the nominal center of the gate and electrode at little cost in process complexity by the provision of a sidewall positioned above the LDD-defining sidewall and extending above the top Of the gate by a buffer amount sufficient to protect the gate during the process of opening a source or drain contact.

Claims

1. A method of forming an LDD transistor in a silicon layer comprising the steps of:

preparing a silicon substrate;

forming a gate stack comprising a gate oxide, a gate electrode layer having a gate top surface and a first sacrificial dielectric;

patterning said gate stack to define a gate stack column having vertical sidewalls and source and drain regions in said silicon layer adjoining said gate stack column;

oxidizing said vertical sidewalls;

depositing a conformal etch resistant dielectric over said gate stack column and said source and drain areas;

depositing a second sacrificial dielectric over said conformal dielectric in said gate stack column and said source and drain areas;

directionally etching horizontal portions of said second sacrificial dielectric and said conformal dielectric, thereby exposing said first sacrificial dielectric and said source and drain areas and leaving first gate sidewalls including at least said conformal dielectric;

removing said first sacrificial dielectric, leaving vertical alignment stubs of said conformal dielectric adjacent extending from said first gate sidewalls above said gate top surface;

depositing a protective conformal dielectric having a nominal contact cover thickness above said gate stack column, thereby forming self-aligned protective members about each of said vertical alignment stubs and having a thickness greater than said nominal contact cover thickness;

depositing a first interlayer dielectric;

etching contact holes above said source and drain regions through said interlayer dielectric and through said protective conformal dielectric to said source and drain regions, whereby a residual thickness of said protective conformal dielectric remains above corners of said gate stack column; and

completing said integrated circuit.

2. A method according to claim 1, in which said first sacrificial dielectric is TEOS.

3. A method according to claim 1, in which said first sacrificial dielectric is boron nitride.

4. A method according to claim 1, further including a step of etching a contact hole above said gate through said protective conformal dielectric to said gate.

5. A method according to claim 4, in which said first sacrificial dielectric is TEOS.

6. A method according to claim 4, in which said first sacrificial dielectric is boron nitride.