Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals
First Claim
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1. A current switching circuit for steering current between a first or second path, said switching circuit comprising:
- a substantially constant current source;
an NMOS device having a source, a drain and a gate, said NMOS source connected to said current source, said NMOS drain connected to said first path and said NMOS gate connected to a control input; and
a PMOS device having a source, a drain and a gate, said PMOS drain connected to said current source, said PMOS source connected to said second path and said PMOS gate connected to said control input;
whereby a logic high at said control input steers current to said first path and a logic low at said control input steers current to said second path.
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Abstract
A current steering switch circuit responsive to a CMOS signal. In an specific embodiment the switch is incorporated in a hybrid BiCMOS multiplexer circuit using combined CMOS and CML/ECL signal types. The high speed CML/ECL logic signals are multiplexed under the control of a lower speed CMOS signal. A particular aspect of the circuit is that a CMOS to CML/ECL converter is not used. Additionally, a differential, logic commutation signal is not required.
65 Citations
10 Claims
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1. A current switching circuit for steering current between a first or second path, said switching circuit comprising:
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a substantially constant current source; an NMOS device having a source, a drain and a gate, said NMOS source connected to said current source, said NMOS drain connected to said first path and said NMOS gate connected to a control input; and a PMOS device having a source, a drain and a gate, said PMOS drain connected to said current source, said PMOS source connected to said second path and said PMOS gate connected to said control input; whereby a logic high at said control input steers current to said first path and a logic low at said control input steers current to said second path. - View Dependent Claims (2, 3, 4)
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5. A BiCMOS multiplexing circuit comprising:
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a substantially constant current source connected to a negative supply; complementary MOS devices comprising an NMOS and a PMOS, each having a drain, a source and a gate, each of said gates adapted to receive an input control signal and said NMOS source and said PMOS drain connected to said current source; first and second differential pairs, each comprising first and second bipolar transistors, each having an emitter, a collector and a base, said emitters of said first bipolar transistors being commonly connected to the drain of said NMOS device, said emitters of said second bipolar transistors being commonly connected to the source of said PMOS device, said base of each of said first and second transistors in each of said first and second differential pairs being adapted to receive CML/ECL input data, said collector of said first transistor in said first differential pair connected to said collector of said first transistor in said second differential pair and said collector of said second transistor in said first differential pair connected to said collector of said second transistor in said second differential pair; first and second load resistors, said first load resistor connected between said collector of said first transistor of said first and second differential pairs and a positive supply, and said second load resistor connected between said collector of said second transistor of said first and second differential pairs and said positive supply; and output means across said load resistor to provide multiplexed data output signals. - View Dependent Claims (6, 7, 8, 9, 10)
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Specification