Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication

• US 5,420,796 A
• Filed: 12/23/1993
• Issued: 05/30/1995
• Est. Priority Date: 12/23/1993
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Weling, Milind, Gabriel, Calvin T.
• Primary Examiner(s): RUGGIERO, JOSEPH F
• Application Number:
  US08/173,581
• Time in Patent Office: 523 Days
• Field of Search: 364/468, 364/488-491, 364/552, 364/562, 364/559, 364/563, 250/491.1, 250/492.1-492.3, 250/234, 250/306, 250/307, 437/7, 437/8
• US Class Current: 438/5
• CPC Class Codes: G01Q 60/24 AFM [Atomic Force Microscopy] or apparatus therefor, e.g. AFM probes
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: Y10S 977/854 Semiconductor sample

Abstract

An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.

Claims

1. A method of controlling an integrated circuit fabrication process, comprising the steps of:

(a) performing a first step of integrated circuit fabrication on a wafer comprising the step of;

forming a first set of one or more material layers on said wafer; and

(b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of;

scanning a predetermined area of said wafer'"'"'s surface with an atomic force microscope;

gathering surface height data from the atomic force microscope representing height with respect to position;

generating from the gathered surface height data at least one signal indicative of surface planarity;

comparing the at least one signal with predefined planarity criteria to determine if said forming step produced a surface that meets said predefined planarity criteria,

2. The method of claim 1, wherein:

said generating step generates said at least one signal using an arithmetic mean procedure.

3. The method of claim 1, wherein:

said generating step generates said at least one signal using a root mean-square procedure.

4. The method of claim 1, wherein:

said generating step generates said at least one signal using a maximum height procedure.

5. The method of claim 1, wherein:

said generating step generates said at least one signal using a peak to valley height procedure.

6. The method of claim 1, wherein:

said generating step generates said at least one signal using a roughness procedure.

7. The method of claim 1, further including:

when the at least one signal is above a predetermined threshold, discarding the wafer;

when the at least one signal is equal to a predetermined threshold, returning the wafer to a prior step of the integrated circuit fabrication for repair; and

when the at least one signal is below a predetermined threshold, continuing with the integrated circuit fabrication process.

8. The method of claim 1, further including:

when the at least one signal is above a predetermined threshold, modifying the fabrication process to increase the quality of subsequent wafer production.

9. The method of claim 1, wherein:

after said second sequence of steps is performed, said first and second sequences of steps are again performed.

10. A method of controlling an integrated circuit fabrication process, comprising the steps of:

(a) performing a first sequence of integrated circuit fabrication steps on a wafer comprising the steps of;

forming and patterning a first set of one or more material layers on said wafer, wherein the first set of layers is deposited and patterned in such manner to create hills and valleys therein;

forming a second set of one or more material layers over said first set of material layers;

etching back the deposited second set of material layers to produce a surface on the resulting wafer;

(b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of;

scanning a predetermined area of said wafer'"'"'s surface with an atomic force microscope;

gathering surface height data from the atomic force microscope representing height with respect to position;

generating from the gathered surface height data at least one signal indicative of surface planarity;

comparing the at least one signal with predefined planarity criteria to determine if said etching back step produced a surface that meets said predefined planarity criteria.

11. The method of claim 10, wherein:

said generating step generates said at least one signal using an arithmetic mean procedure.

12. The method of claim 10, wherein:

said generating step generates said at least one signal using a roughness procedure.

13. The method of claim 10, further including:

when the at least one signal is above a predetermined threshold, discarding the wafer;

when the at least one signal is equal to a predetermined threshold, returning the wafer to a prior step of the integrated circuit fabrication for repair; and

when the at least one signal is below a predetermined threshold, continuing with the integrated circuit fabrication process.

14. The method of claim 10, further including:

when the at least one signal is above a predetermined threshold, modifying the fabrication process of subsequent wafer production.

15. The method of claim 10, wherein:

after said second sequence of steps is performed, said first and second sequences of steps are again performed.

16. A method of controlling an integrated circuit fabrication process, comprising the steps of:

forming and patterning a first material layer on said wafer, wherein the first material layer is deposited and patterned in such manner to create hills and valleys therein;

forming a second material layer over said first material layer;

etching back the deposited second material layer to produce a surface on the resulting wafer;

scanning a predetermined region of the wafer surface with an atomic force microscope;

gathering data from the atomic force microscope representing height with respect to position;

generating from the gathered data at least one signal indicative of surface roughness using a predetermined procedure;

comparing the at least one signal indicative of surface roughness with predefined criteria;

when the at least one signal is below a first predetermined threshold of the predetermined criteria, continuing with the integrated circuit fabrication process;

when the at least one signal is within an intermediate range of said first predetermined threshold and a second predetermined threshold of the predetermined criteria, performing a remedial process on the wafer; and

when the at least one signal is above said second predetermined threshold of the predetermined criteria, discarding the wafer.

17. The method of claim 16, wherein:

said predetermined procedure is an arithmetic mean of the deviations in height from the profile mean procedure.

18. The method of claim 16, wherein:

said predetermined procedure is a root-mean-square procedure.

19. The method of claim 16, further including the step of:

when the at least one signal is above a predetermined threshold, modifying the fabrication process to increase the quality of subsequent wafer production.