Layout method for a semiconductor integrated circuit device

• US 5,420,800 A
• Filed: 09/02/1994
• Issued: 05/30/1995
• Est. Priority Date: 06/26/1990
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fukui, Masahiro
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/300,579
• Time in Patent Office: 270 Days
• Field of Search: 364/491, 364/490, 364/489, 364/488
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method is provided for designing a semiconductor integrated circuit device with optimized shape of blocks to minimize the size of the chip containing the circuit. Design restrictions on the shape and position of each block are determined according to the density of temporary paths for electrical connections between blocks and the shape of each side of each block is optimized within the restrictions. The internal layout of each block is then optimized according to the restrictions.

Claims

1. A method for providing an internal layout of a variable-shape block in a semiconductor integrated circuit device wherein a shape of said variable-shape block can be changed into an irregular shape and said variable-shape block has a plurality of cells, and for optimizing the internal layout of said variable-shape block while satisfying a restriction against the shape of said variable-shape block, said method comprising the steps of:

obtaining the number of cell rows by which the height of said variable-shape block satisfies said restriction;

obtaining the position and length of each of said cell rows in said variable-shape block which satisfies said restriction;

arranging the cells in an optimum cell placement by which each of said number of cell rows can be formed in said length; and

determining paths for wirings between cells.

2. An apparatus for the layout of a semiconductor integrated circuit device wherein one or more blocks are arranged on a chip and wirings for electrical connections are formed in areas in the vicinity of said one or more blocks, said one or more blocks being classified into variable-shape blocks in which a shape thereof can be changed into an irregular shape and fixed-shape blocks in which a shape thereof is fixed,

said apparatus comprising:

means for supposing that each of said one or more blocks has a tentative rectangular shape, and for temporarily optimizing the shape and position of each of said one or more blocks;

means for obtaining temporary paths for said electrical connections;

means for placing restrictions on the shape of each of said variable-shape blocks so as to compensate for the variation in the density of said temporary paths;

means for optimizing the shape of each of said variable-shape blocks by changing said tentative rectangular shape thereof into an irregular shape so as to satisfy said restrictions; and

means for optimizing the internal layout of each of said variable-shape blocks in accordance with said restrictions, thereby minimizing the size of said chips.

3. The apparatus of claim 2 wherein said variable-shape blocks comprise standard cells arranged in a plurality of rows and electrical connections between said one or more blocks are formed in areas in the vicinity of said variable-shape blocks,

said apparatus further comprising means for optimizing the length of each of said rows so as to optimize the shape of each of said variable-shape blocks, thereby minimizing the size of said chip.

4. An apparatus for providing an internal layout of a variable-shape block in a semiconductor integrated circuit device wherein a shape of said variable-shape block can be changed into an irregular shape and said variable-shape block has a plurality of cells, and for optimizing the internal layout of said variable-shape block while satisfying a restriction against the shape of said variable-shape block, said apparatus comprising:

a first means for obtaining the number of cell rows by which the height of said variable-shape block satisfies said restriction;

a second means for obtaining the position and length of each of said cell rows in said variable-shape block which satisfies said restriction;

a third means for arranging the cells in an optimum cell placement by which each of said number of cell rows can be formed in said length obtained by the second means; and

a fourth means for determining paths for wirings between the cells in the optimum cell placement arranged by the third means.

5. A method for optimizing the layout of a semiconductor integrated circuit device wherein one or more blocks are arranged on a chip with wirings for electrical connections formed in areas in the vicinity of said one or more blocks, said one or more blocks being classified into variable-shape blocks in which a shape thereof can be changed into an irregular shape and fixed-shape blocks in which a shape thereof is fixed, whereby the shape of each of said variable-shape blocks is optimized so as to minimize the size of the chip, the method comprising the steps of:

supposing that each of said one or more blocks has a tentative rectangular shape, and temporarily optimizing the shape and position of each of said one or more blocks;

obtaining temporary paths for said electrical connections;

placing restrictions on the shape of each of said variable-shape blocks so as to compensate for the variation in the density of said temporary paths;

optimizing the shape of each of said variable-shape blocks by changing said tentative rectangular shape thereof into an irregular shape so as to satisfy said restrictions; and

optimizing the internal layout of each of said variable-shape blocks in accordance with said restrictions.

6. The method of claim 5 wherein said variable-shape blocks comprise standard cells arranged in a plurality of rows and electrical connections between said one or more blocks are formed in areas in the vicinity of said variable-shape blocks,

said method further comprising the step of optimizing the length of each of said rows so as to optimize the shape of each of said variable-shape blocks.

7. A method for designing a semiconductor integrated circuit device having one or more rectangular blocks arranged on a chip and wirings for electrical connections formed in areas around said one or more blocks, said one or more blocks being classified into variable-shape blocks in which a shape thereof can be changed into an irregular shape and fixed-shape blocks in which a shape thereof is fixed, said method comprising the steps of:

estimating an initial optimum shape and position for each of said one or more blocks;

determining temporary paths for said electrical connections in areas around said one or more blocks;

placing restrictions on the shape of each of said variable-shape blocks according to a wiring density of said temporary paths;

determining an optimum shape for each of said variable-shape blocks by changing said rectangular shape thereof into an irregular shape in accordance with said restrictions, the step of determining the optimum shape further including the steps of dividing the wiring density between adjacent sides of said variable-shape blocks and forming the divided portions of the wiring density with the respective adjacent variable-shape blocks to form a rectangular block shape; and

determining an optimum internal layout for each of said variable-shape blocks in accordance with said restrictions, the step of determining an optimum internal layout being performed by calculating the area of the wiring densities combined within the respective rectangular block shape.

8. The method of claim 7 wherein the step of determining temporary paths for said electrical connections is based upon routing of wiring between said one or more blocks and positions of wiring connection pins on the periphery of said one or more blocks to determine wiring density between said one or more blocks.

9. The method of claim 7 wherein the step of placing restrictions on the shape for each of said variable-shape blocks includes the use of at least one side of one of said fixed-shape blocks as a shape restriction.

10. The method of claim 7 wherein said variable-shape blocks include standard cells arranged in a plurality of rows on a chip and said electrical connections between said one or more blocks are formed around said variable-shape blocks, further comprising the step of determining an optimum length for each of said rows so as to optimize the shape of each of said variable-shape blocks to minimize the overall size of said chip.

11. A method for designing an internal layout of a variable-shape block in a semiconductor integrated circuit device wherein a shape of said variable-shape block can be changed into an irregular shape and said variable-shape block has a plurality of cells arranged in rows, and for optimizing the shape of said variable-shape block while satisfying a restriction against the shape of said variable-shape block, the method comprising the steps of:

(a) determining the number of cell rows which satisfies a restriction on the height of said variable-shape block;

(b) determining the position and length of each of said cell rows in said variable-shape block which satisfies said restriction;

(c) ascertaining an optimum placement of each cell within said length of each cell row determined in step (b) and arranging the respective cells in the optimum placement; and

(d) ascertaining paths for wirings between the cells in the optimum placement arranged in step (c).