Multiplication circuit for multiplying analog inputs by digital inputs

• US 5,420,807 A
• Filed: 08/10/1994
• Issued: 05/30/1995
• Est. Priority Date: 10/19/1993
• Status: Expired due to Fees

• Current Assignee: YOZAN, Inc.
• Original Assignee: YOZAN, Inc.
• Inventors: Yamamoto, Makoto, Takatori, Sunao, Shou, Guoliang, Yang, Weikang
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/288,077
• Time in Patent Office: 293 Days
• Field of Search: 364/606, 364/602, 364/841, 328/160
• US Class Current: 708/7
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A multiplication circuit for multiplying an analog input by a digital input. The digital input has a plurality of bits. The circuit has a circuit input terminal for receiving the analog input and a circuit output terminal for outputting the results of multiplication of the analog input by the digital input. The circuit also has a plurality of capacitances and a plurality of switching devices.

Claims

1. A multiplication unit comprising:

a unit input terminal for receiving an analog input;

a unit output terminal for outputting a result of multiplication of the analog input by a plurality of digital inputs, each digital input having a plurality of bits;

a first multiplication circuit, which is connected to the unit input terminal; and

a second multiplication circuit, which is connected to the unit output terminal and the first multiplication circuit;

wherein the first and second multiplication circuits each comprise;

a circuit input terminal for receiving an analog signal;

a circuit output terminal;

a plurality of capacitors, each being commonly connected to the circuit output terminal; and

a plurality of switching means, each being connected to one of the capacitors and each being commonly connected to the circuit input tereminal, for selectively outputting the analog signal, each switching means having a control terminal for receiving one of the bits of one of the digital inputs.

2. A multiplication unit comprising:

a unit input terminal for receiving an analog input;

a unit output terminal for outputting a result of multiplication of the analog input by a sum of a plurality of digital inputs, each digital input having a plurality of bits;

a first multiplication circuit, which is connected to the unit input terminal and the unit output terminal; and

a second multiplication circuit, which is connected to the unit input terminal and the unit output terminal;

wherein the first and second multiplication circuits each comprise;

a plurality of capacitors, each being commonly connected to the unit output terminal; and

a plurality of switching means, each being connected to one of the capacitors and each being commonly connected to the unit input tereminal, for selectively outputting the analog input, each switching means having a control terminal for receiving one of the bits of one of the digital inputs.

3. A multiplication unit according to claim 2, further comprising:

first stabalization means, connected between the first multiplication circuit and the unit output terminal, for producing a stabalized result of multiplication of the analog input by one of the digital inputs; and

second stabalization means, connected between the second multiplication circuit and the unit output terminal, for producing a stabalized result of multiplication of the analog input by one of the digital inputs.

4. A multiplication unit according to claim 3, further comprising:

a first output capacitor, which is connected between the first stabalization means and the unit output terminal; and

a second output capacitor, which is connected between the second stabalization means and the unit output terminal.

5. A multiplication unit comprising:

a first unit input terminal for receiving a first analog input;

a second unit input terminal for receiving a second analog input;

a unit output terminal for outputting a result of a sum of multiplication of the first analog input by a first digital input and multiplication of the second analog input by a sum of a second digital and a third digital input, the first, second and third digital inputs each having a plurality of bits;

a first multiplication circuit, which is connected to the first unit input terminal and the unit output terminal;

a second multiplication circuit, which is connected to the second unit input terminal; and

a third multiplication circuit, which is connected to the second multiplication circuit and the unit output terminal;

wherein the first, second and third multiplication circuits each comprise;

a circuit input terminal for receiving an analog signal;

a circuit output terminal;

a plurality of capacitors, each being commonly connected to the circuit output terminal; and

a plurality of switching means, each being connected to one of the capacitors and each being commonly connected to the circuit input tereminal, for selectively outputting the analog signal, each switching means having a control terminal for receiving one of the bits of one of the first, second, or third digital inputs.