Processing commands and data in a common pipeline path in a high-speed computer graphics system

• US 5,421,028 A
• Filed: 03/31/1994
• Issued: 05/30/1995
• Est. Priority Date: 03/15/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Swanson, Roger W.
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US08/221,271
• Time in Patent Office: 425 Days
• Field of Search: 395/163, 395/375, 395/650, 395/775, 395/800
• US Class Current: 712/42
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A pipelined processing system in which context switching for each of the pipelined processing circuits within the pipeline may be accomplished without flushing the data from the pipeline. This is accomplished by sending the pipeline commands and data together through the pipeline and differentiating the commands from the data using a flag added to the commands and data which specifies whether the associated data word is a command or data. During operation of the pipeline, when the input data is received by one of the pipelined processing circuits in the pipeline, the flag is checked to see if the associated data word includes a command. If the associated data word includes data to be processed, it is processed in accordance with the current configuration of the pipeline. However, if the associated data word includes a command for setup and control and the like, each pipelined processing circuit within the pipeline compares its identification value with a tag field in the command to determine whether it is to be reconfigured by that command. If it is to be reconfigured by that command, the appropriate context switching and the like takes place. However, if the current pipelined processing circuit is not to be reconfigured by that command, that command is passed through the current pipelined processing circuit unprocessed so that a similar determination may be made by the next pipelined processing circuit in the pipeline. As a result, setup and control commands for the pipelined processing circuits may be passed through the data processing pipeline along with the data in the desired processing order such that a pipeline data flush is not necessary between reconfigurations of the pipelined processing circuits. Since the pipeline need not be flushed when processes are changed, processing efficiency and throughput are substantially improved.

Claims

1. A pipelined processing system for sequentially processing a plurality of data blocks including only system data or pipeline setup and control commands and associated setup and control data, comprising:

a data processing pipeline having at least two pipelined processing circuits which perform predetermined functions on data blocks input thereto, each pipelined processing circuit including means for reading predetermined bits of received data blocks and for processing system data and pipeline setup and control commands and associated setup and control data within read data block which said pipelined processing circuit is authorized to process; and

means for providing data blocks having a predetermined number of bits to said data processing pipeline, each data block including means read by said reading means of each pipelined processing circuit for indicating whether that data block contains a pipeline setup and control command, each data block containing a pipeline setup and control command further comprising identifying means read by said reading means of each pipelined processing circuit for identifying whether said pipelined processing circuit is authorized to process that pipeline setup and control command, said providing means providing said pipeline setup and control commands in said data blocks in the desired order for processing by said pipelined processing circuits such that a pipeline data flush is not necessary between reconfigurations of said pipelined processing circuits.

2. A system as in claim 1, wherein each pipelined processing circuit checks said indicating means in each data block received at an input thereof to determine if the present data block contains data or a data processing command and, if the present data block contains a data processing command, said pipelined processing circuit checks said identifying means to determine if a data processing command of the present data block is to be processed by said pipelined processing circuit.

3. A system as in claim 2, wherein each pipelined processing circuit passes through unprocessed those data processing commands which said identifying means indicates are not to be processed by said pipelined processing circuit.

4. A system as in claim 1, wherein each pipelined processing circuit has an identification value and said identifying means comprises a tag field containing a tag value which is compared by said processing means of said pipelined processing circuit to said identification value to determine whether said pipelined processing circuit is to be reconfigured by a pipeline setup and control command for processing of subsequent system data.

5. A pipelined graphics processing system for sequentially processing a plurality of data blocks including only graphics data or pipeline setup and control commands and associated setup and control data, comprising:

a graphics pipeline having at least two pipelined processing circuits which perform predetermined functions on data blocks input thereto, each pipelined processing circuit including means for reading predetermined bits of received data blocks and for processing graphics data and pipeline setup and control commands and associated setup and control data within read data blocks which said pipelined processing circuit is authorized to process; and

means for providing data blocks having a predetermined number of bits to said graphics pipeline, each data block including means read by said reading means of each pipelined processing circuit for indicating whether that data block contains a pipeline setup and control command, each data block containing a pipeline setup and control command further comprising identifying means read by said reading means of each pipelined processing circuit for identifying whether said pipelined processing circuit is authorized to process that pipeline setup and control command, said providing means providing said pipeline setup and control commands in said data blocks in the desired order for processing by said pipelined processing circuits such that a pipeline data flush is not necessary between reconfigurations of said pipelined processing circuits.

6. A system as in claim 5, wherein each pipelined processing circuit checks said indicating means in each data block received at an input thereof to determine if the present data block contains graphics data or a graphics data processing command and, if the present data block contains a graphics data processing command, said pipelined processing circuit checks said identifying means to determine if a graphics data processing command of the present data block is to be processed by said pipelined processing circuit.

7. A system as in claim 6, wherein each pipelined processing circuit passes through unprocessed those graphics data processing commands which said identifying means indicates are not to be processed by said pipelined processing circuit.

8. A system as in claim 5, wherein each pipelined processing circuit has an identification value and said identifying means comprises a tag field containing a tag which is compared by said processing means of said pipelined processing circuit to said identification value to determine whether said pipelined processing circuit is to be reconfigured for processing of subsequent graphics data.

9. A system as in claim 5, wherein said graphics pipeline includes a polygon processor, a pixel processor, a pixel cache and a frame buffer connected in series.

10. A method of sequentially processing a plurality of data blocks including only system data or pipeline setup and control commands and associated setup and control data in a data processing pipeline having at least two pipelined processing circuits which perform predetermined functions on data blocks input thereto, each pipelined processing circuit including means for reading predetermined bits of received data blocks and for processing system data and pipeline setup and control commands and associated setup and control data within read data blocks which said pipelined processing circuit is authorized to process, comprising the steps of:

inputting data blocks having a predetermined number of bits to a first of said pipelined processing circuits, said pipeline setup and control commands being provided in said data blocks in the desired order for processing by said pipelined processing circuits such that a pipeline data flush is not necessary between reconfigurations of said pipelined processing circuits; and

for each pipelined processing circuit of said data processing pipeline, performing the steps of;

said reading means determining whether an input data block contains a pipeline setup and control command, and, if the input data block contains a pipeline setup and control command, further determining whether the current pipelined processing circuit is authorized to process that pipeline setup and control command, and

if the current pipelined processing circuit is authorized to process the pipeline setup and control command in the input data block, said processing means of the current pipelined processing circuit processing that pipeline setup and control command and passing results of the processing of that pipeline setup and control command to the next pipelined processing circuit in the data processing pipeline, but if the current pipelined processing circuit is not authorized to process the pipeline setup and control command in the input data block, said processing means passing the input data block containing the pipeline setup and control command through the current pipelined processing circuit unprocessed to the next pipelined processing circuit in the data processing pipeline.

11. A method as in claim 10, wherein the step of determining whether the current pipelined processing circuit comparing an indentification value of the current pipelined processing circuit with a tag in a tag field in the input command.