Process for forming a static-random-access memory cell

• US 5,422,296 A
• Filed: 04/25/1994
• Issued: 06/06/1995
• Est. Priority Date: 04/25/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lage, Craig S.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/232,968
• Time in Patent Office: 407 Days
• Field of Search: 437/48, 437/52, 437/56, 437/57, 437/89, 437/203, 257/330, 257/332, 257/393, 257/903
• US Class Current: 438/212
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

Claims

1. A process for forming a static-random-access memory cell comprising the steps of:

providing a substrate including;

a semiconductor base material having a first conductivity type;

a buried oxide layer overlying the semiconductor base material;

a first doped region overlying the buried oxide layer, wherein the first doped region has a second conductivity type that is opposite the first conductivity type; and

a first semiconductor layer overlying the first doped region and having the first conductivity type;

forming a second doped region, wherein the second doped region;

has the second conductivity type; and

lies within the first semiconductor layer;

forming a first trench extending through the buried oxide layer, first doped region, first semiconductor layer, and second doped region, wherein;

the first trench has a wall surface, a bottom surface, and a central region; and

a channel region of a first transistor lies within the first semiconductor layer adjacent to the wall surface of the first trench;

forming a second semiconductor layer overlying the semiconductor base material within the central region of the first trench, wherein;

the second semiconductor layer has the second conductivity type;

the second semiconductor layer has a wall surface that faces the wall surface of the first trench; and

a channel region of a second transistor lies within the second semiconductor layer and adjacent to the wall surface of the second semiconductor layer;

forming a third doped region lying within the second semiconductor layer and having the first conductivity type;

forming a first gate dielectric layer lying adjacent to the wall surface of the first trench and second semiconductor layer and adjacent to the bottom surface of the first trench outside of the central region of the first trench; and

forming a first conductive member, wherein the first conductive member;

lies at least partially within the first trench and adjacent to the first gate dielectric layer;

laterally surrounds the second semiconductor layer; and

acts as a shared-gate electrode for the first and second transistors.

2. The process of claim 1, further comprising steps of:

electrically connecting the semiconductor base material to a V_DD electrode; and

electrically connecting the first doped region to a V_SS electrode.

3. The process of claim 1, wherein the step of forming second semiconductor layer includes epitaxially growing silicon.

4. The process of claim 1, wherein:

the step of forming the second doped region also forms a fourth doped region, wherein the second and fourth doped regions;

have the second conductivity type;

lie within the first semiconductor layer; and

are spaced apart from each other;

the step of forming the first trench also forms a second trench, wherein;

the second trench extends through the buried oxide layer, first doped region, first semiconductor layer and the fourth doped region;

the second trench has a wall surface, a bottom surface, and a central region; and

a channel region of a third transistor lies within the first semiconductor layer adjacent to the wall surface of the second trench;

the step of forming the second semiconductor layer includes forming a portion of the second semiconductor layer overlying the semiconductor base material within the central region of the second trench, wherein;

the portion of second semiconductor layer has the second conductivity type;

the portion of the second semiconductor layer has a wall surface that faces the wall surface of the second trench; and

a channel region of a fourth transistor lies within the second semiconductor layer adjacent to the wall surface of the second trench;

the step of forming a third doped region also forms a fifth doped region lying within the portion of the second semiconductor layer that lies within the second trench and having the first conductivity type;

the step of forming a first gate dielectric layer also forms a second gate dielectric layer, wherein the second gate dielectric layer lies adjacent to the wall surface of the second trench and the portion of the second semiconductor layer within the second trench and adjacent to the bottom surface of the second trench outside of the central region of the second trench;

the step of forming the first conductive member also forms a second conductive member, wherein;

the second conductive member lies at least partially within the second trench and adjacent to the second gate dielectric layer;

the second conductive member has laterally surrounds the portion of the second semiconductor layer lying within the second trench; and

the second conductive member acts as a shared-gate electrode for a third transistor and a fourth transistor; and

the process further comprises steps of;

forming a sixth doped region and a seventh doped region, wherein the sixth and seventh doped regions;

have the second conductivity type;

lie within the first semiconductor layer; and

are spaced apart from each other and the second and fourth doped regions; and

forming at least one third conductive member, wherein the at least one third conductive member;

overlies portions of the second, fourth, sixth, and seventh doped regions, a portion of the first semiconductor layer that lies between the second and sixth doped regions, and another portion of the first semiconductor layer that lies between the fourth and seventh doped regions; and

acts as gate electrodes for access transistors.

5. The process of claim 4, wherein the step of forming second semiconductor layer includes epitaxially growing silicon.

6. The process of claim 1, wherein the step of forming the second semiconductor layer is performed by depositing a material selected from a group consisting of polysilicon and amorphous silicon.

7. The process of claim 1, further comprising steps of:

forming a spacer adjacent to the wall surface of the first trench prior to the step of forming the second semiconductor layer; and

removing the spacer after the step of forming the second semiconductor layer.

8. The process of claim 7, wherein the spacer includes oxide.

9. A process for forming a static-random access memory cell comprising the steps of:

providing a semiconductor substrate including;

a semiconductor base material having a first conductivity type;

a buried oxide layer overlying the semiconductor base material;

a first doped region overlying the buried oxide layer, wherein the first doped region has a second conductivity type that is opposite the first conductivity type; and

a first semiconductor layer overlying the first doped region and having the first conductivity type;

forming a second doped region and a third doped region, wherein the second and third doped regions;

have the second conductivity type;

lie within the first semiconductor layer; and

are spaced apart from each other;

forming a first trench and a second trench wherein;

the first trench extends through the buried oxide layer, first doped region, first semiconductor layer, and the third doped region;

the second trench extends through the buried oxide layer, first doped region, first semiconductor layer, and the second doped region;

each of the first and second trenches has a wall surface, a bottom surface, and a central region;

a channel region of a first latch transistor lies within the first semiconductor layer adjacent to the wall surface of the first trench; and

a channel region of a second latch transistor lies within the first semiconductor layer adjacent to the wall surface of the second trench;

forming a second semiconductor layer overlying the semiconductor material, wherein;

a first portion of the second semiconductor layer is formed within the central region of the first trench and has a wall surface that faces the wall surface of the first trench;

a second portion of the second semiconductor layer is formed within the central region of the second trench and has a wall surface that faces the wall surface of the second trench;

the second semiconductor layer has the second conductivity type;

a channel region of a first load transistor lies adjacent to the wall surface of the first portion; and

a channel region of a second load transistor lies adjacent to the wall surface of the second portion;

forming a fourth doped region and a fifth doped region, wherein;

the fourth doped region lies within the first portion of the second semiconductor layer;

the fifth doped region lies within the second portion of the second semiconductor layer; and

the fourth and fifth doped regions have the first conductivity type;

forming a first gate dielectric layer and a second gate dielectric layer, wherein;

the first gate dielectric layer lies adjacent to the wall surfaces of the first trench and the first portion of the second semiconductor layer and adjacent to the bottom surface of the first trench outside of the central region of the first trench; and

the second gate dielectric layer lies adjacent to the wall surfaces of the second trench and the second portion of the second semiconductor layer and adjacent to the bottom surface of the second trench outside of the central region of the second trench;

forming a first conductive member and a second conductive member, wherein;

the first conductive member;

lies at least partially within the first trench and adjacent to the first gate dielectric layer;

laterally surrounds the first portion of the second semiconductor layer; and

acts as a shared-gate electrode for the first latch and first load transistors; and

the second conductive member;

lies at least partially within the second trench and adjacent to the second gate dielectric layer;

laterally surrounds the second portion of the second semiconductor layer; and

acts as a shared-gate electrode for the second latch and second load transistors;

forming a sixth doped region and a seventh doped region, wherein the sixth and seventh doped regions;

have the second conductivity type;

lie within the first semiconductor layer; and

are spaced apart from each other and the second and third doped regions; and

forming at least one third conductive member, wherein the at least one third conductive member;

overlies portions of the second, third, sixth, and seventh doped regions, a portion of the first semiconductor layer that lies between the second and sixth doped regions, and another portion of the first semiconductor layer that lies between the third and seventh doped regions; and

acts as gate electrodes for access transistors.

10. The process of claim 9, wherein the step of forming second semiconductor layer includes epitaxially growing silicon.

11. The process of claim 9, further comprising steps of:

electrically connecting the semiconductor base material to a V_DD electrode; and

electrically connecting the first doped region to a V_SS electrode;

electrically connecting the sixth doped region to a first bit line; and

electrically connecting the seventh doped region to a second bit line.

12. The process of claim 9, wherein:

the step of providing includes the semiconductor base material having a p-type dopant concentration in a range of 1E17 to 1E18 atoms per cubic centimeter, the first doped region having an n-type dopant concentration of at least 1E19 atoms per cubic centimeter, and the first semiconductor layer has a p-type dopant concentration no higher than 1E17 atoms per cubic centimeter;

the steps of forming the second, third, sixth, and seventh doped regions each include doping portions of the first semiconductor layer with an n-type dopant to a dopant concentration of at least 1E19 atoms per cubic centimeter;

the step of forming the second semiconductor layer forms a silicon layer having an n-type dopant concentration no higher than 1E17 atoms per cubic centimeter; and

the step of forming the fourth and fifth doped regions are formed by doping part of the first and second portions, respectively, of the second semiconductor layer with a p-type dopant to a dopant concentration of at least 1E19 atoms per cubic centimeter.

13. The process of claim 9, wherein the step of forming the second semiconductor layer is performed by depositing a material selected from a group consisting of polysilicon and amorphous silicon.

14. The process of claim 9, further comprising steps of:

forming spacers adjacent to the wall surfaces of the first and second trenches prior to the step of forming the second semiconductor layer; and

removing the spacers after the step of forming the second semiconductor layer.

15. The process of claim 14, wherein the spacers include oxide.