BiCDMOS structure

• US 5,422,508 A
• Filed: 03/05/1993
• Issued: 06/06/1995
• Est. Priority Date: 09/21/1992
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Jun W., Williams, Richard K., Yilmaz, Hamza, Cornell, Michael E.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Fahmy, Wael M.
• Application Number:
  US08/026,930
• Time in Patent Office: 823 Days
• Field of Search: 257/335, 257/336, 257/337, 257/369, 257/370, 257/338, 257/372, 257/577
• US Class Current: 257/370
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/7322 having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/009 Bi-MOS
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Claims

1. A lateral transistor structure, comprising:

a first semiconductor layer being of a semiconductor material of a first conductivity type;

a second semiconductor layer disposed on said first semiconductor layer, said second semiconductor layer having an upper surface;

a field oxide layer disposed on said upper surface of said second semiconductor layer;

a field implant region disposed underneath said field oxide layer, said field implant region being of a semiconductor material of said first conductivity type, said field implant region being lightly doped;

a drain region extending into said second semiconductor layer from said upper surface of said second semiconductor layer, said drain region contacting said field implant region, said drain region being of a semiconductor material of said first conductivity type;

a source region extending into said second semiconductor layer from said upper surface of said second semiconductor layer, said source region being laterally separated from said field implant region, said source region being of a semiconductor material of said first conductivity type;

a body contact region extending into said second semiconductor layer from said upper surface of said second semiconductor layer, said body contact region contacting said source region, said source region being disposed between said body contact region and said field implant region, said body contact region being of a semiconductor material of a second conductivity type opposite said first conductivity type;

a body region extending from said body contact region and underneath said source region, said body region extending between said source region and said field implant region to form a channel region at said upper surface of the second semiconductor layer between said source region and said field implant region, said body region being separated from said field implant region by a drift region portion of said second semiconductor layer between said source region and said field implant region, said body contact region being of a semiconductor material of said second conductivity type; and

a polysilicon gate layer, said polysilicon gate layer extending from a location over said source region, over said channel region, and over said drift region portion of said second semiconductor layer.

2. The lateral transistor structure of claim 1, wherein said first semiconductor layer is an epitaxial layer, and wherein said second semiconductor layer is a well region of a semiconductor material of said second conductivity type extending downward into said first semiconductor layer.

3. The lateral transistor structure of claim 1, wherein said second semiconductor layer is of an epitaxial semiconductor material of said first conductivity type, said second semiconductor layer being less heavily doped than said first semiconductor layer, said first semiconductor layer being a substrate layer.

13. The lateral transistor structure of claim 1, wherein said channel region of said body region is counterdoped by a blanket implantation step.

14. The lateral transistor structure of claim 13, wherein said blanket implantation step involves a dose of phosphorous of approximately 0.5-5.0 E12 cm².

15. The lateral transistor structure of claim 14, wherein said body region is ion implanted with a dose of boron before said blanket implantation step, said dose of boron being approximately 0.5-1.5 E14 cm².

4. A lateral transistor structure, comprising:

a substrate layer of a semiconductor material of a first conductivity type;

an epitaxial layer of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer disposed over said substrate layer, said epitaxial layer having an upper surface;

a first buried region extending downward into said substrate layer and also extending upward into said epitaxial layer, said first buried region having an upper surface disposed below said upper surface of said epitaxial layer, said first buried region being of a semiconductor material of said second conductivity type;

a drain region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said drain region being of a semiconductor material of said second conductivity type;

a sinker region extending downward into said epitaxial layer from said drain region, said sinker region contacting said buried region, said sinker region being of a semiconductor material of said second conductivity type;

a lightly doped drain region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said lightly doped drain region contacting said drain region and extending laterally over said first buried region along said upper surface of said epitaxial layer from said drain region, said lightly doped drain region being of a semiconductor material of said second conductivity type, said lightly doped drain region being more lightly doped than said drain region;

a body region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said body region being of a semiconductor material of said first conductivity type, said body region being separated from said lightly doped drain region by a drift region portion of said epitaxial layer;

a source region extending downward into said body region from said upper surface of said epitaxial layer, said source region being separated from said drift region portion of said epitaxial layer by a channel region of said body region, said source region being of a semiconductor material of said second conductivity type;

a body contact region extending downward into said body region from said upper surface of said epitaxial layer, said body contact region being separated from a channel region of said body region by said source region, said body contact region being of a semiconductor material of said first conductivity type; and

a polysilicon gate layer disposed over said channel region and over said drift region portion of said epitaxial layer.

5. The lateral transistor structure of claim 4, further comprising:

a second buried region, said second buried region extending downward into said substrate layer and also extending upward into said epitaxial layer, said second buried region being laterally separated from said first buried region, said second buried region having an upper surface disposed below said upper surface of said epitaxial layer, said second buried region being of a semiconductor material of said first conductivity type; and

an isolation sinker region extending downward into said epitaxial layer, said isolation sinker region contacting said second buried region, said isolation sinker region being of a semiconductor material of said first conductivity type.

6. The lateral transistor structure of claim 4, further comprising:

a second buried region, said second buried region extending downward into said substrate layer and also extending upward into said epitaxial layer, said second buried region being laterally separated from said first buried region so that said second buried region surrounds said first buried region in a laterally oriented plane, said second buried region having an upper surface disposed below said upper surface of said epitaxial layer, said second buried region being of a semiconductor material of said first conductivity type; and

an isolation sinker region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said isolation sinker region contacting said second buried region so that said isolation sinker region surrounds said sinker region, said lightly doped drain region, said drain region, said body region, said source region, and said body contact region in said laterally oriented plane, said isolation sinker region being of a semiconductor material of said first conductivity type.

7. The lateral transistor structure of claim 6, further comprising:

a field oxide layer and an underlying field implant region, said field oxide layer being at least partly disposed between said isolation sinker region and said body region.

8. The lateral transistor structure of claim 6, wherein said body region contacts said isolation sinker region.

9. The lateral transistor structure of claim 4, wherein said lightly doped drain region is formed by blanket implantation with dopant ions of said second conductivity type.

10. The lateral transistor structure of claim 9, wherein said channel region of said body region is counterdoped by said blanket implantation.

11. The lateral transistor structure of claim 9, wherein said blanket implantation is a dose of phosphorous of approximately 0.5--5.0 E12 cm².

12. The lateral transistor structure of claim 11, wherein said body region is ion implanted with a dose of boron before said blanket implantation, said dose of boron being approximately 0.5-1.5 E14 cm².