High voltage negative charge pump with low voltage CMOS transistors

• US 5,422,590 A
• Filed: 04/26/1994
• Issued: 06/06/1995
• Est. Priority Date: 01/05/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lin, Sung-Wei, Coffman, Tim M.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/234,433
• Time in Patent Office: 406 Days
• Field of Search: 307/296.2, 307/241, 307/296.1, 307/264, 307/270, 307/296.6, 365/189.09, 323/14, 363/59, 363/60, 327/536, 327/537
• US Class Current: 327/537
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A system for erasing a memory array in a memory has a supply voltage and a negative charge pump. The negative charge pump system includes (a) circuitry to select a memory array to be erased; (b) for circuitry to switch on the supply voltage Vnn for the charge pump; (c) circuitry to pump the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) circuitry to erase the selected array with the pumped negative voltage; (e) circuitry to provide the pumping; and (f) circuitry to provide a discharge path for voltages trapped in the charge pump.

Claims

1. A negative-voltage charge pump connected to a supply voltage, the pump having an input, an output, and a plurality of multiplier stages connected between the input and the Gattput, the pump comprising:

(a) a discharge circuit connected between a high voltage trap node and a lesser potential discharge node at each multiplier stage; and

(b) a dual polarity switch circuit for allowing switching between positive and negative voltages, said dual polarity switch connected to at least those said discharge circuits of the last of said multiplier stages.

2. The negative-voltage charge pump of claim 1, further comprising:

(a) initialization circuits connected between a majority of said multiplier stages and the supply voltage, and

b) an initialization control circuit connected between the initialization circuits and the supply voltage, including means for lowering the breakdown voltage of the drain, source and substrate (BVDSS) requirement for the initialization control circuit.

3. The negative-voltage charge pump of claim 1, further comprising a substrate switching circuit in at least two multiplier stages, the substrate switching circuit connected between substrates of transistors and the supply voltage, the substrate switching circuit including means for lowering the breakdown voltage of the drain, source and substrate (BVDSS) requirement for the substrate switching circuit.

4. The charge pump of claim 1 wherein the discharge circuits comprise:

(a) a first plurality of discharge circuits, wherein each discharge circuit of the first plurality comprises two transistors having their source-drain electrodes connected in series, and the gate of one of the transistors connected to the dual polarity switch; and

(b) a second plurality of discharge circuits and, wherein each discharge circuit of the second plurality comprises three transistors having their source-drain electrodes connected in series, and the gates of two of the transistors connected to the dual polarity switch.

5. The charge pump of claim 1 wherein the dual polarity switch circuit comprises:

(a) a control logic level shifter; and

(b) a voltage switch.

6. The charge pump of claim 4 wherein the discharge circuits further comprise a third plurality of discharge circuits, wherein each discharge circuit of the third plurality comprises three transistors having their source-drain electrodes connected in series in a MOS diode stack.

7. The negative charge pump of claim 5, further comprising:

(a) initialization circuits connected between a majority of said multiplier stages and the supply voltage, and

(b) an initialization control circuit connected between the initialization circuits and the supply voltage, including means for lowering the breakdown voltage of the drain, source and substrate (BVDSS) requirement for the initialization control circuit.

8. The negative-voltage charge pump of claim 5, further comprising a substrate switching circuit in at least two multiplier stages, the substrate switching circuit connected between substrates of transistors and the supply voltage, the substrate switching circuit including means for lowering the breakdown voltage of the drain, source and substrate (BVDSS) requirement for the substrate switching circuit.

9. The charge pump of claim 5 wherein the discharge circuits comprise:

(a) a first plurality of discharge circuits, each discharge circuit of said first plurality comprising two transistors having their source-drain electrodes connected in series, and the gate of one of the transistors connected to the voltage switch; and

(b) a second plurality of discharge circuits, each discharge circuit of said second plurality comprising three transistors having their source-drain electrodes connected in series, and the gates of two of the transistors connected to the voltage switch.

10. The charge pump of claim 9 wherein the discharge circuits further comprise a third plurality of discharge circuits, wherein each discharge circuit of the third plurality comprises three transistors having their source-drain electrodes connected in series in a MOS diode stack.

11. The charge pump of claim 5 wherein the control logic level shifter comprises:

(a) first and second P-channel transistors, a first source-drain electrode of the first P-channel transistor connected to a first source-drain electrode of the second P-channel transistor,

(b) a first N-channel transistor connected between a second source-drain electrode of the first P-channel transistor and ground, and

(c) second and third N-channel transistors, a first source-drain electrode of the second N-channel transistor connected to a first source-drain electrode of the third N-channel transistor, a second source-drain electrode of the second N-channel transistor connected to the gate of the first N-channel transistor, and a second source-drain electrode of the third N-channel transistor connected to the gate of the first P-channel transistor.

12. The charge pump of claim 5 wherein the voltage switch comprises:

(a) third and fourth P-channel transistors, a first source-drain electrode of the third P-channel transistor connected to a first source-drain electrode of the fourth P-channel transistor, a second source-drain electrode of the third P-channel transistor connected to the control logic level shifter, a second source-drain electrode of the fourth P-channel transistor connected to a supply voltage; and

(b) a fifth P-channel transistor having a first source-drain electrode connected to ground, a second source-drain electrode connected to the gate of the fourth P-channel transistor, and a substrate connected to the substrate of the third P-channel transistor.

13. The charge pump of claim 11 wherein the voltage switch comprises:

(a) third and fourth P-channel transistors, a first source-drain electrode of the third P-channel transistor connected to a first source-drain electrode of the fourth P-channel transistor, a second source-drain electrode of the third P-channel transistor connected to a second source-drain electrode of the second P-channel transistor, a second source-drain electrode of the fourth P-channel transistor connected to a supply voltage, the substrate of the fourth P-channel transistor connected to the substrate of the second P-channel transistor; and

(b) a fifth P-channel transistor having a first source-drain electrode connected to ground, a second source-drain electrode connected to the gate of the fourth P-channel transistor, and a substrate connected to the substrate of the third P-channel transistor.