Amplifier input stage with charge pump supplying a differential transistor pair

• US 5,422,600 A
• Filed: 06/23/1994
• Issued: 06/06/1995
• Est. Priority Date: 06/23/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Petty, Thomas D., Vyne, Robert L., Stockstad, Troy L.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/264,290
• Time in Patent Office: 348 Days
• Field of Search: 307/296.1, 307/296.6, 330/252, 330/257, 330/261, 330/288, 330/296
• US Class Current: 330/257
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 2203/45124 the folded cascode stage of the folded cascode dif amp being a current mirror
• CPC Class Codes: H03F 2203/45476 the CSC comprising a mirror circuit
• CPC Class Codes: H03F 2203/45648 the LC comprising two current sources, which are not cascode current sources
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 3/45094 Folded cascode stages

Abstract

An input stage to an amplifier circuit (10) operating with a one volt power supply potential (32) receives a differential input signal. A charge pump (36) increases the one volt power supply potential to 1.8 volts for providing additional head-room for the differential input signal. A current source (44) controls a current mirror (40-42) to draw a predetermined current from the charge pump to supply the active conduction path of a differential transistor pair (12-14). An output stage (34) of the amplifier circuit operates off the one volt power supply potential. Since the charge pump drives only the differential transistor pair through the current mirror, it may be made small to fit on the same integrated circuit as the amplifier including any necessary pump capacitors.

Claims

1. An input stage of amplifier circuit, comprising:

a differential transistor pair operating in response to a differential input signal for developing first and second voltages;

circuit means responsive to said first and second voltages for providing an output signal of the input stage of the amplifier circuit;

a charge pump coupled for receiving an operating potential from a first power supply conductor and having an output for providing a pump voltage;

a first current source for providing a predetermined current at an output; and

a current mirror circuit having first and second conduction paths, said first conduction path being coupled between said output of said first current source and said output of said charge pump, said second conduction path being coupled between said output of said charge pump and a conduction path of said differential transistor pair.

2. The amplifier circuit of claim 1 further including an output stage operating in response to said output signal from the input stage for providing an output signal of the amplifier, said output stage being coupled for receiving said operating potential from said first power supply conductor.

3. The input stage of claim 2 wherein said current mirror circuit includes:

a first transistor having a base, an emitter and a collector, said base and said collector being coupled together to said output of said first current source, said emitter being coupled to said output of said charge pump; and

a second transistor having a base, an emitter and a collector, said base being coupled to said base and said collector of said first transistor, said emitter being coupled to said output of said charge pump, said collector being coupled to said conduction path of said differential transistor pair.

4. The input stage of claim 2 wherein said current mirror circuit includes a first transistor having a base, an emitter and first and second collectors, said base and said first collector being coupled together to said output of said first current source, said emitter being coupled to said output of said charge pump, said second collector being coupled to said conduction path of said differential transistor pair.

5. The input stage of claim 3 wherein said first current source includes a third transistor having a base, an emitter, a collector, said collector being coupled to said base and said collector of said first transistor, said base being coupled for receiving a first reference potential, said emitter being coupled to a second power supply conductor.

6. The input stage of claim 5 wherein said differential transistor pair includes:

a fourth transistor having a base, an emitter and a collector, said emitter being coupled to said collector of said second transistor;

a first resistor coupled between said collector of said fourth transistor at a first node and said second power supply conductor for developing said first voltage;

a fifth transistor having a base, an emitter and a collector, said bases of said fourth and fifth transistors being coupled for receiving said differential input signal, said emitter being coupled to said collector of said second transistor; and

a second resistor coupled between said collector of said fifth transistor at a second node and said second power supply conductor for developing said second voltage.

7. The input stage of claim 6 wherein said circuit means includes:

a second current source for providing second and third currents of predetermined magnitude at first and second outputs respectively;

a sixth transistor having a base, an emitter and a collector, said emitter being coupled to said first node, said base and said collector being coupled to said first output of said second current source; and

a seventh transistor having a base, an emitter and a collector, said base being coupled to said base and said collector of said sixth transistor, said emitter being coupled to said second node, said collector being coupled to said second output of said second current source, said collector being further coupled to said input of said output stage for providing said output signal of the input stage of the amplifier circuit.

8. The input stage of claim 7 wherein said second current sources includes:

an eighth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base being coupled for receiving a second reference potential, said collector being coupled to said collector and said base of said sixth transistor; and

a ninth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base being coupled for receiving said second reference potential, said collector being coupled to said collector of said seventh transistor.

9. An amplifier circuit, comprising:

a differential transistor pair operating in response to a differential input signal for developing first and second voltages;

circuit means responsive to said first and second voltages for providing an output signal of the input stage of the amplifier circuit;

a charge pump coupled for receiving an operating potential from a first power supply conductor and having an output for providing a pump voltage;

a first current source for providing a predetermined current at an output;

a first transistor having a base, an emitter and a collector, said base and said collector being coupled together to said output of said first current source, said emitter being coupled to said output of said charge pump;

a second transistor having a base, an emitter and a collector, said base being coupled to said base and said collector of said first transistor, said emitter being coupled to said output of said charge pump, said collector being coupled to a conduction path of said differential transistor pair; and

an output stage operating in response to said output signal from the input stage for providing an output signal of the amplifier, said output stage being coupled for receiving said operating potential from said first power supply conductor.

10. The amplifier circuit of claim 9 wherein said first current source includes a third transistor having a base, an emitter, a collector, said collector being coupled to said base and said collector of said first transistor, said base being coupled for receiving a first reference potential, said emitter being coupled to a second power supply conductor.

11. The amplifier circuit of claim 10 wherein said differential transistor pair includes:

a fourth transistor having a base, an emitter and a collector, said emitter being coupled to said collector of said second transistor;

a first resistor coupled between said collector of said fourth transistor at a first node and said second power supply conductor for developing said first voltage;

a fifth transistor having a base, an emitter and a collector, said bases of said fourth and fifth transistors being coupled for receiving said differential input signal, said emitter being coupled to said collector of said second transistor; and

a second resistor coupled between said collector of said fifth transistor at a second node and said second power supply conductor for developing said second voltage.

12. The input stage of claim 11 wherein said circuit means includes:

a second current source for providing second and third currents of predetermined magnitude at first and second outputs respectively;

a sixth transistor having a base, an emitter and a collector, said emitter being coupled to said first node, said base and said collector being coupled to said first output of said second current source; and

a seventh transistor having a base, an emitter and a collector, said base being coupled to said base and said collector of said sixth transistor, said emitter being coupled to said second node, said collector being coupled to said second output of said second current source, said collector being further coupled to said input of said output stage for providing said output signal of the input stage of the amplifier circuit.

13. The input stage of claim 12 wherein said second current sources includes:

an eighth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base being coupled for receiving a second reference potential, said collector being coupled to said collector and said base of said sixth transistor; and

a ninth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base being coupled for receiving said second reference potential, said collector being coupled to said collector of said seventh transistor.

14. An input stage of amplifier circuit, comprising:

a differential transistor pair operating in response to a differential input signal for developing first and second voltages;

circuit means responsive to said first and second voltages for providing an output signal of the input stage of the amplifier circuit;

a charge pump coupled for receiving an operating potential from a first power supply conductor and having an output for providing a pump voltage;

a first current source for providing a predetermined current at an output; and

a first transistor having a base, an emitter and first and second collectors, said base and said first collector being coupled together to said output of said first current source, said emitter being coupled to said output of said charge pump, said second collector being coupled to said conduction path of said differential transistor pair.

15. The amplifier circuit of claim 14 further including an output stage operating in response to said output signal from the input stage for providing an output signal of the amplifier, said output stage being coupled for receiving said operating potential from said first power supply conductor.

16. The input stage of claim 15 wherein said first current source includes a second transistor having a base, an emitter, a collector, said collector being coupled to said base and said first collector of said first transistor, said base being coupled for receiving a first reference potential, said emitter being coupled to a second power supply conductor.

17. The input stage of claim 16 wherein said differential transistor pair includes:

a third transistor having a base, an emitter and a collector, said emitter being coupled to said second collector of said first transistor; and

a fourth transistor having a base, an emitter and a collector, said bases of said third and fourth transistors being coupled for receiving said differential input signal, said emitter being coupled to said second collector of said first transistor.

18. The input stage of claim 17 wherein said circuit means includes:

a fifth transistor having a base, an emitter and a collector, said collector being coupled to said collector of said third transistor at a first node for developing said first voltage, said base being coupled for receiving said first reference potential, said emitter being coupled to said second power supply conductor; and

a sixth transistor having a base, an emitter and a collector, said collector being coupled to said collector of said fourth transistor at a second node for developing said second voltage, said base being coupled for receiving said first reference potential, said emitter being coupled to said second power supply conductor.

19. The input stage of claim 18 wherein said circuit means further includes:

a current mirror circuit having an input and an output;

a seventh transistor having a base, an emitter and a collector, said collector being coupled to said input of said current mirror circuit, said base being coupled for receiving a second reference potential, said emitter being coupled to said first node; and

an eighth transistor having a base, an emitter and a collector, said collector being coupled to said output of said current mirror circuit at said input of said output stage for providing said output signal of the input stage of the amplifier circuit, said base being coupled for receiving said second reference potential, said emitter being coupled to said second node.

20. The input stage of claim 19 wherein said current mirror circuit includes:

a ninth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base and said collector being coupled together to said collector of said seventh transistor; and

a tenth transistor having a base, an emitter and a collector, said emitter being coupled to said first power supply conductor, said base being coupled to said base and said collector of said ninth transistor, said collector being coupled to said collector of said eighth transistor at said input of said output stage.