Data stream converter with increased grey levels

• US 5,422,654 A
• Filed: 03/18/1994
• Issued: 06/06/1995
• Est. Priority Date: 10/17/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Tjandrasuwita, Ignatius B., Margeson, James E. III
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): Au, A.
• Application Number:
  US08/210,257
• Time in Patent Office: 445 Days
• Field of Search: 348/89, 348/98, 348/99, 348/103, 348/147, 348/104, 348/214, 348/3
• US Class Current: 345/103
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 5/366 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04N 3/127 using liquid crystals

Abstract

The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Claims

1. A frame buffer system for displaying data on a dual panel display, the dual panel display including an upper panel and a lower panel, the frame buffer system for receiving a cathode ray tube (CRT) data frame having an upper half and a lower half, the frame buffer system for displaying current upper and lower panel refresh frames and next upper and lower panel refresh frames generated from the CRT data frame, the frame buffer system comprising:

first means for generating a gray level pattern from the CRT data frame for the current upper and lower panel refresh frames;

second means for generating a gray level pattern from the CRT data frame for the next upper and lower panel refresh frames;

means coupled to the first generating means for providing the current upper panel refresh frame to the upper panel, responsive to a first state of a control signal and for providing the current lower panel refresh frame to the lower panel responsive to a second state of a control signal;

means for delaying the next panel refresh frame; and

means coupled to the second generating means and the delaying means for providing the delayed next lower panel refresh frame to the lower panel responsive to the first state of a control signal and for providing the delayed next upper panel refresh frame to the upper panel responsive to the second state of a control signal.

2. The frame buffer system of claim 1 in which the current panel refresh frame providing means comprises a first multiplexer and the delayed next panel refresh frame providing means comprises a second multiplexer.

3. The frame buffer system of claim 1 in which includes:

means for controlling the first and second providing means.

4. The frame buffer system of claim 1 in which the delaying means comprises a half-frame buffer.

5. The frame buffer system of claim 1 in which the first generating means and the second generating means generate the current panel refresh frame and the next panel refresh frame simultaneously.

6. A half frame buffer system for displaying data on a dual panel display, the dual panel display including an upper panel and a lower panel, the frame buffer system for receiving a cathode ray tube (CRT) data frame and the frame buffer system for displaying a current upper and lower panel refresh frames and next upper and lower panel refresh frames generated from the CRT data frame, the frame buffer system comprising:

a first means for generating gray level patterns from the CRT data frame for the current upper and lower panel refresh frames;

a second means for generating gray level patterns from the CRT data frame for the next upper and lower panel refresh frame;

a half frame buffer coupled to the second means for delaying the next panel refresh frame;

a first multiplexer for providing the current upper panel refresh frame to the upper panel responsive to a first state of a control signal and for providing the current lower panel refresh frame to the lower panel responsive to a second state of the control signal; and

a second multiplexer means coupled to the half frame buffer for providing the delayed next upper panel refresh frame to the lower panel responsive to the first state of the first control signal and for providing the delayed next lower panel refresh frame to the lower panel responsive to a second state of the control signal during the lower half of the CRT data frame.