Apparatus and method for processing a picture-in-picture video signal

• US 5,422,677 A
• Filed: 08/25/1993
• Issued: 06/06/1995
• Est. Priority Date: 08/25/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Do, Young S.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Cohen, Cheryl
• Application Number:
  US08/111,498
• Time in Patent Office: 650 Days
• Field of Search: 348/565-568
• US Class Current: 348/568
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen

Abstract

The present invention relates to an apparatus and method for processing a picture-in-picture video signal for PIP display of a compressed sub-picture displayed within a main picture on advanced TV receivers. More particularly, the present invention relates to the apparatus and method for processing a PIP video signal of advanced TV systems which use real video data lines, as opposed to artifically generated lines of video data, as the interleaving line to interleave the present field being compressed, when vertically compressing a sub-picture video signal. Accordingly, the present invention provides a hardware of simple constitution and a PIP display with advanced resolution.

Claims

1. An apparatus for processing a picture-in-picture (PIP) video signal, the apparatus comprising:

a memory for storing a sub-picture signal and reading out the stored sub-picture signal;

a vertical compressing unit for receiving a horizontal synchronizing signal synchronized with the sub-picture signal and for controlling said memory to store lines of the sub-picture signal by units of two subsequent lines and to not store an associated line of the two lines;

a controller for inputting to said memory a predetermined write clock and a read clock, the read clock having a speed faster than the write clock, in a ratio proportional to the horizontal compression of the sub-picture; and

a composite processor for composing the compressed sub-picture signal read from said memory in conformity to the video signal of a main picture and the read clock;

wherein said vertical compressing unit comprises

a binary counter for synchronizing with the horizontal synchronization signal of the sub-picture signal and counting the horizontal synchronization signal, said counter being reset when a binary counting value reaches a predetermined value; and

an inverter, connected between an output terminal of said binary counter and a write enable terminal of said memory, for inverting an output value of said binary counter.

2. The apparatus for processing a PIP video signal according to claim 1, further comprising an A/D converter for converting the sub-picture signal to a digital signal and inputting the converted signal to said memory.

3. The apparatus for processing a PIP video signal according to claim 2, further comprising a low pass filter coupled between said A/D converter and said memory, for preventing aliasing of a vertical frequency of the sub-picture signal.

4. The apparatus for processing a PIP video signal according to claim 2, wherein a D/A converter, connected between said memory and said composite processor, converts digital data read from said memory into an analog signal.

5. The apparatus for processing a PIP video signal according to claim 1, wherein said memory is a field memory for storing the sub-picture data in field units.

6. The apparatus for processing a PIP video signal according to claim 1, wherein said apparatus is incorporated in a television unit employing high definition signal processing.

7. A circuit for vertical compression of a video signal, the circuit comprising:

a field memory for storing and reading the video signal in field units; and

a vertical compressing unit for synchronizing with a horizontal synchronization signal of the video signal and repeatedly controlling said field memory to store the lines of the video signal in units of two subsequent lines and to not store a line related to the two lines stored;

wherein said vertical compressing unit further comprises

a binary counter for counting the horizontal synchronization signal, said counter being reset when a binary counting value attains a given value; and

an inverter, connected between an output terminal of said binary counter and a write enable terminal of said field memory, for inverting an output value of said binary counter.